1988-06-17
1989-12-26
James, Andrew J.
357 42, 357 71, H01L 2978
Patent
active
048901423
ABSTRACT:
The invention relates to a structure of parallel power MOS transistors, each of which comprises on a common face of a substrate gate, source and drain contact zones and three levels of the connection layers. The first level of connection layers (20) establishes a contact with all the gates and a connection between each gate and the adjacent gates. A second level of the connection layers establishes a contact with all the source regions (22) and drain regions (23) and a connection between each source (or drain) region and the adjacent source (or drain) regions, and has apertures insulating each drain (or source) contact. A third continuous level of the connection layer level (25) establishes a contact with all the drain (or source) regions of the second level of the connection layers.
REFERENCES:
patent: 4589004 (1986-05-01), Yasuda et al.
patent: 4612565 (1986-09-01), Shimizu et al.
patent: 4631705 (1986-12-01), Honda
Thomas Gilles
Tonnel Eugene
James Andrew J.
Prenty Mark
SGS-Thomson Microelectronics S.A.
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