Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Patent
1996-01-16
1997-12-02
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
257208, 257211, 257401, 257412, 257413, H01L 2710
Patent
active
056939663
ABSTRACT:
Propagation delay times of an input signal from an input terminal to respective gates are equalized and accelerated with a power MOS transistor that includes a plurality of transistor blocks. The transistor blocks are formed by sources being connected to each other by a first electric conductive layer (8.sub.2, 8.sub.4, 8.sub.6 and 10), drains being connected to each other by a second electric conductive layer (8.sub.1, 8.sub.3, 8.sub.5 and 9), and gates (6) consisting of a continuous semiconductor layer. The transistor has a third electric conductive layer (11) being connected to a gate terminal Gin and laminated on the gates. The third electric conductive layer laminated on the gates functions to equalize and accelerate propagation delay times of an input signal from an input terminal to the respective gates. By extending that conductive layer to near the center of a principal plane of the gate, the delay time of a gate input signal to the transistor block located at the center of the semiconductor chip can be reduced substantially.
REFERENCES:
patent: 5256894 (1993-10-01), Shino
patent: 5341014 (1994-08-01), Fujii et al.
patent: 5486715 (1996-01-01), Zommer
Anazawa Takeo
Fukazawa Hidetaka
Coleman Sharon K.
Mintel William
Motorola Inc.
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