Power MOS device chip and package assembly

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...

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Details

257723, 257719, 257341, 257343, H01L 2348, H01L 23051, H01L 2932

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active

058216162

ABSTRACT:
A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection. The terminal is placed in mechanical and electrical contact with the contact washer.

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