Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2002-07-08
2004-10-05
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
Reexamination Certificate
active
06800934
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
A related patent application is a commonly assigned Japanese Patent Application No. 2001-240738 filed on Aug. 8, 2001, which is incorporated by reference into the present patent application.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power module, and more particularly to a power module having a plurality of insulated gate bipolar transistors (IGBTs) arranged in parallel with each other.
2. Description of the Related Art
FIG. 4
is a schematic view of a conventional power module indicated in its entirety as
500
. The power module
500
includes a ceramic substrate
501
. On the ceramic substrate
501
, an emitter electrode pattern
502
, a collector electrode pattern
503
, and a gate electrode pattern
504
are provided in substantially parallel with each other. At each one end of the electrode patterns
502
,
503
, and
504
, an emitter lead
512
, a collector lead
513
, and a gate lead
514
are provided, respectively.
Onto the collector electrode pattern
503
, two insulated gate bipolar transistors (IGBTs)
521
and
522
are fixed. Each back face of the IGBTs
521
and
522
is a collector electrode. Each of the collector electrodes is electrically connected to the collector electrode pattern
503
. Emitter electrodes on the front faces of the IGBTs
521
and
522
are connected to the emitter electrode pattern
502
, via bonding wires
523
and
524
, respectively. Gate electrodes on the IGBTs
521
and
522
are connected to the gate electrode pattern
504
via bonding wires
525
and
526
, respectively. Furthermore, an emitter electrode on the IGBT
521
is connected to a ground electrode
528
, via a bonding wire
527
. Typically, a cover is placed over the ceramic substrate
501
to seal the IGBT
521
and other components. However, the cover is omitted in this drawing.
FIG. 5
shows a layout of the emitter electrode pattern
502
and the collector electrode pattern
503
of the power module of FIG.
4
. In
FIG. 5
, like reference numerals refer to similar or corresponding parts shown in FIG.
4
.
In such power module
500
, the two IGBTs
521
and
522
are arranged in parallel with each other. Feeding signals into the gate electrode pattern
504
allows simultaneous switching of the two IGBTs
521
and
522
, thereby supplying large current between the emitter electrode pattern
502
and the collector electrode pattern
503
.
However, when the IGBTs
521
and
522
are switched, the inductance components generate counter electromotive force in the bonding wires
525
and
526
, and the emitter electrode pattern
502
.
First, suppose that electric potential at each point of P, Q, R, and S shown in
FIG. 5
is 0 V (ground potential) in the initial state.
Next, the IGBTs
521
and
522
are switched using the bonding wires
525
and
526
, respectively, and brought to the ON state. Immediately after switching, current flows from the point P to the point Q, from the point Q to the point R, and from the point S to the point R. Then, current flows through the emitter electrode pattern
502
in the direction shown by an arrow
530
. At the same time, the inductance components cause voltage drop between the points P and Q, and the other points. As a result, unbalanced conditions occur in the gate-to-emitter voltages on the IGBTs
521
and
522
. These unbalanced conditions cause a timing lag of switching the IGBTs
521
and
522
.
For example, suppose that the electric potential at the point P is 0 V. Then, the electric potential at the point Q is −3 V and that at the point R is −5 V because of the influence of the voltage drop. On the other hand, voltage increases in the direction from the point R to the point S, and thus the electric potential at the point S is −2 V. Therefore, the gate-to-emitter voltages on the IGBTs
521
and
522
have different values of 15 V and 17 V respectively, immediately after the electric potential at the both gates are set to 15 V. This phenomenon causes a timing lag of switching the two IGBTs
521
and
522
. Such a timing lag results in excessive load imposed on one of the IGBTs, which has been one of causes of failures and shorter lives of the IGBTs.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a power module having a plurality of IGBTs arranged in parallel with each other and switched at the same timing.
The present invention provides a power module having a plurality of power devices arranged in parallel with each other and switched by gate signals with substantially equal electric potential. The power module includes: a collector electrode pattern, first and second power devices provided on the collector electrode pattern and each having a collector electrode connected to the collector electrode pattern; an emitter electrode pattern provided along the collector electrode pattern and having an emitter lead, and first and second connection means for connecting emitter electrodes on the first and second power devices and the emitter electrode pattern, respectively. The power module is characterized in that an inductance component of at least one of the first and second connection means is adjusted so that the inductance component between the emitter electrode on the first power device and the emitter lead is substantially equal to that between the emitter electrode on the second power device and the emitter lead.
Also, the present invention provides a power module further including: a third power device provided on the collector electrode pattern in symmetrical relation with the first power device so as to sandwich the second power device together, and having a collector electrode connected to the collector electrode pattern, and a third connection means for connecting an emitter electrode on the third power device and the emitter electrode pattern. The emitter lead is provided substantially in the center of the emitter electrode pattern so that the inductance component between the emitter electrode on the first power device and the emitter lead is substantially equal to that between the emitter electrode on the third power device and the emitter lead. The inductance component of the second connection means is adjusted so that the inductance component between the emitter electrode on the second power device and the emitter lead is substantially equal to that between the emitter electrode on the first power device and the emitter lead.
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patent: 5642253 (1997-06-01), Shreve
patent: 5763946 (1998-06-01), Nakadaira et al.
patent: 5767576 (1998-06-01), Kobayashi et al.
patent: 6100728 (2000-08-01), Shreve et al.
patent: 6479327 (2002-11-01), Takahashi et al.
patent: 6541838 (2003-04-01), Suetsugu et al.
patent: 19938302 (1998-08-01), None
patent: 58-23469 (1983-02-01), None
patent: 61-139051 (1986-06-01), None
patent: 6-334066 (1994-02-01), None
patent: 8-340082 (1996-12-01), None
patent: 11-238851 (1999-08-01), None
patent: 2001-7282 (2001-01-01), None
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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