Power management for low power processors through the use of aut

Details Power management for low power processors through the use of aut Power management for low power processors through the use of aut

1993-03-24

1996-12-17

Ray, Gopal C.

Boots, shoes, and leggings

364707, 3642731, 3642732, 3642733, 3642624, 364DIG1, G06F 132

Patent

active

055863329

ABSTRACT:
A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.

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