Power linearizer of a CDMA system and method thereof

Amplifiers – Hum or noise or distortion bucking introduced into signal...

Reexamination Certificate

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C330S129000, C330S136000

Reexamination Certificate

active

06642785

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CDMA system, and more particularly, to a power linearizer of a CDMA system.
2. Background of the Related Art
In general, a radio frequency band amplifier using active elements generates many undesired distortion components according to a change of a power level.
Especially when the amplifier is operated in the vicinity of a saturation area, a non-linear phenomenon remarkably appears to distort an amplitude and a phase of an output, and when more than two signals are inputted, inter-modulation distortion (MD) components are generated between the input signals, having much influence on the adjacent channel.
The IMD components work as a noise source to degrade a transmission quality of a communication system and reduce a capacity of the CDMA system.
FIG. 1
is a schematic block diagram of a related art power linearizer of a CDMA system. As shown therein, the related art power linearizer includes an input unit
10
for converting a digital input signal (s[n]) into an analog signal(s(t)), a linearization amplifying controller
20
for performing an amplification control to remove a non-linear characteristic of a power amplifier
30
, and a power amplifier
30
for amplifying a power of an input signal (s(t)) inputted from the input unit
10
under the control of the linearization amplifying controller
20
.
The input unit
10
includes a multiplier
11
for multiplying the digital input signal (s[n]) and a transmission gain signal (g[n]) together, and a digital-to-analog converter
12
for converting the digital signal outputted from the multiplier
11
to an analog signal.
The linearization amplifying controller
20
includes a multiplier
21
for multiplying power control information (c[n]), which controls an increase and decrease of amplification, and a power control step (P) indicative of an increased or decreased power value. It further includes an accumulator
22
for accumulating an output signal of the multiplier
21
, an adder
23
for adding a digital output signal of the accumulator
22
and an adjust gain (a[n]) for removing a non-linear characteristic of the power amplifier
30
, and a digital-to-analog converter
24
for converting the digital signal outputted from the adder
23
into an amplification control signal of an analog form.
The power control information c[n] has a control value of 1 or 2 in digital form. One control value increases the power as high as a specified value and the other control value decreases the power as low as a specified value. The specified power value refers to the power control step (P).
The multiplier
21
of the linearization amplifying controller
20
multiplies the power control information c[n] and the power control step (P), and the accumulator
22
accumulates the output signal of the multiplier
21
.
The adder
23
adds the output signal of the accumulator
22
and the adjust gain (a[n]) and outputs an amplification control signal for controlling amplification of the power amplifier
30
so as to remove a non-linear characteristic of the power amplifier
30
. The adjust gain a[n] is a value to adjust the amplification so that the non-linear power amplifier
30
may have a linearity. The value of a[n] used for generating the amplification control signal to remove the non-linear characteristic of the power amplifier
30
is critical.
The digital/analog converter
24
of the linearization amplifying controller
20
converts the output signal of the adder
23
into an analog form, and generates an analog amplification control signal (v(t)) to control an amplification level of the power amplifier
30
.
The multiplier
11
of the input unit
10
multiplies the digital input signal (s[n]) and the transmission gain signal (g[n]), and the digital/analog converter
12
of the input unit
10
converts the digital signal outputted from the multiplier
11
into an analog signal s(t) and outputs it to the power amplifier
30
.
The power amplifier
30
amplifies the power of the output signal s(t) of the digital/analog converter
12
according to the analog amplification control signal (v(t)) outputted from the digital/analog converter
24
of the linearization amplifying controller
20
.
FIG. 2
is a graph showing power characteristic curves of a power linearizer in accordance with the related art amplifier. As shown, PA(V) indicates an actual power characteristic curve of the power amplifier
30
, PB(V) indicates a required linear power characteristic curve, and PC(V) indicates a power compensation curve to remove the non-linear characteristic.
In the CDMA system, in order to minimize the influence on the adjacent channel and increase the subscriber accommodation capacity, each mobile terminal should use the minimum power.
With reference to
FIG. 2
, on the assumption that a desired power is P
2
, when the power amplifier
30
has a linear characteristic, V
1
is to be applied to the power amplifier
30
as a value of the input signal. However, when the voltage of V
1
is inputted, the power amplifier
30
outputs a power of P
1
according to the non-linear characteristic.
Accordingly, the power of P
2
should be obtained through the power compensation. That is, as shown in the output characteristic of the power amplifier
30
, an input voltage of V
2
is necessary to output the accurate P
2
.
Thus, the value of V
1
~V
2
is compensated by using a value of the amplification control signal v(t) of the power amplifier
30
, and the value of the adjust gain a[n] used for generating the corresponding amplification control signal v(t) is to be generated.
The value of a[n] is computed by using a difference value between a requested input voltage according to the linearization characteristic curve for outputting a desired power and an actual input voltage according to a nonlinear characteristic curve for outputting the desired power. The conventional power linearizer has the adjust gain a[n], that is, the compensation value for outputting a desired power, in a table form. Accordingly, a value to be compensated at an arbitrary point (an input voltage) is computed by linearly interpolating a corresponding value stored in the table.
The power linearizer of the related art has many problems. For example, the conventional power linearizer should have a slope of a straight line for interpolation and an offset value, and a power compensation value at an arbitrary position of the equation of the straight line should be computed, which makes it complicated to implement the power linearizer.
In addition, the conventional power linearizer compensates the power by adjusting the amplification control signal of the amplifier as much as an error between the linear power (a requested power) and the non-linear power. In this respect, the amplification control signal controls the amplification of the power amplifier in an analog format. Since analog signals are influenced by noise, it is difficult to accurately control the power.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a power linearizer of a CDMA system that is capable of accurately and easily compensating a non-linearity of a voltage controlled power amplifier (VCA).
Another object of the present invention is to provide a power linearizer of a CDMA system that is capable of increasing a capacity of the CDMA system by controlling a digital gain of the VCA.
To achieve at least the above objects in whole or in part and in accordance with the purpose of the invention, as embodied and broadly described herein, there is prov

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