Power line coupling prevention circuit for semiconductor memory

Details Power line coupling prevention circuit for semiconductor memory Power line coupling prevention circuit for semiconductor memory

1996-10-31

1998-08-25

Nelms, David C.

Static information storage and retrieval

Powering

365206, G11C 702

Patent

active

057989770

ABSTRACT:
A power line coupling prevention circuit for a semiconductor memory device which has a plurality of memory cell arrays and supply and ground voltage lines formed between adjacent ones of the memory cell arrays. The power line coupling prevention circuit comprises a capacitor formed between the supply and ground voltage lines, and a switching device connected to the capacitor, for making the capacitor conductive. The switching device is operated in response to a data output buffer enable control signal, The capacitor has one side connected to one of the supply and ground voltage lines and the other side connected to the switching device. The switching device is adapted to control the connection of the capacitor between the supply and ground voltage lines in a read operation. Therefore, a voltage level on the ground voltage line can be prevented from increasing due to the coupling between the supply and ground voltage lines

REFERENCES:
patent: 5173875 (1992-12-01), Komatsu
patent: 5280450 (1994-01-01), Nakagome et al.
patent: 5287241 (1994-02-01), Puar
patent: 5396454 (1995-03-01), Nowak
patent: 5535152 (1996-07-01), Han
patent: 5596474 (1997-01-01), Wada

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