Power latch circuit for computer self deactivation

Details Power latch circuit for computer self deactivation Power latch circuit for computer self deactivation

1986-11-14

1987-08-04

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

361110, 361 92, 361 56, H02H 324

Patent

active

046850236

ABSTRACT:
A power latch circuit uses first and second bipolar transistors responsive to an actuate voltage to latch into a conductive state with power supplied to a computer and a third bipolar transistor powered by the latch circuit and responsive to a deactivate voltage from the computer to place the first and second transistors in a deactivated state to remove power from the computer and itself. It further uses an FET in parallel with the third bipolar transistor and activated directly from the DC power supply when the second transistor is deactivated to latch the first and second transistors in the deactivated state in spite of voltage fluctuations on the deactivate line which might otherwise cause the latch circuit to reactivate. As an FET, it uses little current through its gate compared to alternative bipolar devices while the latch circuit is deactivated.

REFERENCES:
patent: 4402294 (1983-07-01), McHugh et al.
patent: 4520418 (1985-05-01), Susi
patent: 4568096 (1986-02-01), Yeu et al.
Horowitz, The Art of Electronics, Cambridge University Press 1980, pp. 357, 358, 514, 515.

Affiliated with

Also associated with

Rating

Power latch circuit for computer self deactivation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power latch circuit for computer self deactivation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power latch circuit for computer self deactivation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-887009