Power inverter designed to minimize switching loss

Details Power inverter designed to minimize switching loss Power inverter designed to minimize switching loss

2002-09-18

2004-02-10

Nguyen, Matthew V. (Department: 2838)

Electric power conversion systems

Current conversion

With condition responsive means to control the output...

C363S132000, C318S801000

Reexamination Certificate

active

06690593

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to a power inverter working to drive a polyphase load, and more particularly to such a power inverter designed to minimize a switching loss.
2. Background Art
FIG. 13
shows an example of an electrical structure of a typical inverter working to drive a polyphase AC motor used in driving an electric vehicle. The inverter main circuit
7
is made up of six IGBTs
1
to
6
which are joined in the form of a three-phase bridged connection. The inverter main circuit
7
has DC buses
7
a
and
7
b
connected to a positive terminal and a negative terminal of the drive battery
8
, respectively, and output terminals
7
u
,
7
v
, and
7
w
connected to respective phase windings (not shown) of a three-phase AC motor such as a synchronous motor, an induction motor, or a brushless motor. The freewheeling diodes D
1
to D
6
are connected between a collector and an emitter of the IGBTs
1
to
6
electrically in a reverse parallel.
The command generator
10
includes a ROM storing therein data on voltage commands U*, V*, and W* and is designed, for example, to measure a zero-cross point of an output of a current sensor (not shown) disposed between each of the output terminals
7
u
to
7
w
of the inverter main circuit
7
and one of windings of the polyphase AC motor
9
, measure a phase &thgr; of a rotor of the AC motor
9
using an output of a rotary encoder or a resolver, read the voltage commands U*, V*, and W* for three phases (will also be referred to as U, V, and W-phases below) out of the ROM based on the phase &thgr; to output them to the PWM-waveform generator
11
. Note that each of the voltage commands U*, V*, and W* is a function of amplitude of a sine wave, for example.
FIG. 14
shows an internal structure of the PWM-waveform generator
11
. The voltage commands U*, V*, and W* are inputted from the command generator
10
to non-inverting inputs of comparators
12
a
,
12
c
, and
12
e
and to inverting inputs of comparators
12
b
,
12
d
, and
12
f
. The carrier wave generator
13
produces a carrier wave in the form of a triangular wave for pulse width modulation (PWM) and outputs it to the inverting inputs of the comparators
12
a
,
12
c
, and
12
e
and the non-inverting inputs of the comparators
12
b
,
12
d
, and
12
f
, respectively.
In a case where the voltage commands U*, V*, and W* and the carrier wave are provided in a digital form, each of the comparators
12
a
to
12
f
is implemented by a magnitude comparator. Alternatively, in a case where they are all provided in an analog form, each of the comparators
12
a
to
12
f
is implemented by an analog comparator.
When the voltage commands U*, V*, and W* are higher in level than the carrier wave, the comparators
12
a
,
12
c
, and
12
e
output signals C
1
, C
3
, and CS of a high level to the dead time generator
14
. Simultaneously, the comparators
12
b
,
12
d
, and
12
f
output signals C
2
, C
4
, and C
6
that are reversed in level to signals C
1
, C
3
, and C
5
to the dead time generator
14
, respectively. The dead time generator
14
works to correct on-off timing of the signals C
1
, C
2
, C
3
, C
4
, C
5
, and C
6
so as to produce a dead time during which ones of the IGBTs
1
to
6
that are on a negative and a positive side on one arm are both in an off-state in order to prevent the both are in an on-state simultaneously.
The dead time generator
14
produces gate signals G
1
′ to G
6
′ which are inputted to gates of the IGBTs
1
to
6
as gate signals G
1
to G
6
, respectively, through the driver
15
made by, for example, a photocoupler.
Considering, as an example, the U-phase, when the voltage command U* is higher in level than the carrier wave, the IGBT
1
is turned on, while the IGBT
2
is turned off, so that a potential at a positive side of a DC power supply (i.e., the battery
8
) is outputted from the inverter main circuit
7
. Conversely, when the voltage command U* is lower in level than the carrier wave, the IGBT
1
is turned off, while the IGBT
2
is turned on, so that a potential at a negative side of the DC power supply is outputted from the inverter main circuit
7
. With these operations, the voltage on the positive side of the battery
8
is outputted during a time period that is proportional to the voltage command U* in a cycle of the carrier wave.
If each of the voltage commands U*, V*, and W* is, as shown in FIGS.
15
(
a
) and
15
(
b
), in the form of a sine wave, the voltage is outputted from the inverter main circuit
7
in the form of a sine wave into which the width of pulses is modulated, thereby outputting the current in the form of substantially a sine wave. As the frequency of the carrier wave is increased, it becomes possible to have the output current approach an ideal sine wave. Increasing the frequency of the carrier wave to 15 kHz or more results in a great decrease in magnetic noise of the motor
9
. To this end, the inverter main circuit
7
uses the IGBTs
1
to
6
which are capable of being switched on and off at high speed.
The inverter main circuit
7
, however, has a drawback in that operating the inverter main circuit
7
on a great power causes a great amount of heat to be generated due to a loss of power conversion, thus requiring cooling it using water, for example, which forms the obstruction to miniaturization and reduction in manufacturing cost of the system. Half of the loss of power conversion is attributed to an on-off switching loss of the IGBTs
1
to
6
. The switching loss usually increases with an increase in switching frequency, thus encountering a difficulty in using the IGBTs
1
to
6
at high switching frequencies.
In order to avoid such a problem, Japanese Patent Application No. 11-369662 (U.S. Pat. No. 6,324,085 B2 assigned to the same assignee as that of this application) teaches a system designed to disenable switching operations of transistors of the inverter main circuit temporarily for a given period of time so as to minimize distortion of waveform of an output current for decreasing the switching loss.
Specifically, during a period of time X, as shown in FIG.
16
(
b
), in which any two of the voltage commands U*, V*, and W* are, as shown in FIGS.
16
(
a
) to
17
(
f
), nearly equal to each other, the above system works to fix the two of the voltage commands U*, V*, and W* at a maximum or a minimum value to stop the switching operation. The period of time X contains a first cycle (b, d, f) in which he two of the voltage commands U*, V*, and W* are fixed at the maximum or minimum value and a second cycle (a, c, e, g) in which only one of the voltage commands U*, V*, and W* is fixed at the maximum or minimum value which are provided alternately, thereby resulting in a further decrease in distortion of the waveform of the output current as well as reducing the switching loss.
The above system, however, determines the switching disenabling period of time regardless of the level of the output current, so that the switching, as shown in FIGS.
18
(
a
) and
18
(
b
), may be performed during a period of time in which the amount of current flowing to a load is relatively great, thus resulting in a difficulty in reducing the switching loss sufficiently.
SUMMARY OF THE INVENTION
It is therefore a principal object of the invention to avoid the disadvantages of the prior art.
It is another object of the invention to provide a power inverter for a polyphase load designed to minimize an on-off switching loss of switching elements installed in the inverter.
According to one aspect of the invention, there is provided a power inverter designed to output power to a polyphase load. The power inverter comprises: (a) an inverter main circuit working to apply phase voltages to the polyphase load through switching elements; (b) a voltage command outputting circuit outputting first voltage commands for respective phases, each of the first voltage commands varying between a maximum and a minimum level; (c) a voltage command c

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