Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-10-11
2003-06-03
Le, N. (Department: 2858)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06573767
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of a detector circuit, and particularly to power down detecting and voltage zeroing circuits.
BACKGROUND OF THE INVENTION
A problem in many integrated circuits is the elimination of latent voltages in the power-down state. There are many functions which may be needed to perform at initial power-down such as storing critical data.
This is particularly useful for server class computer systems, RAID (redundant array of independent disks) systems that sense voltage and power levels in cluster modules before re-powering, and battery-backed or battery operated integrated circuits, which may be used to perform power-management or nonvolatizing functions for an electronic system. If the power bus is not properly discharged, spurious data may be created and erroneous commands to the system may be issued. Thus, a great many types of systems and integrated circuits include a power-on-reset circuit to detect when power is applied after a power-down condition.
A power-on-reset (POR) cell is a circuit that outputs a logical “1” or “0” signal when the power supply voltage, the input to the POR, has reached a sufficient, valid level. The POR output switches to a logical “1” or “0” for a determined time when the supply voltage reaches a predetermined voltage level, returning to a non-active logic state after the determined time. A POR cell is useful because many circuits require the application of a master reset signal only after the supply voltage reaches a valid signal. When the supply voltage reaches a valid level, the master reset signal can start all clocks and bring the active elements of a system to a known state so that proper operation can begin.
One problem in POR circuits is power cycling. Power cycling involves turning the supply on and off repeatedly, for example, while remaining as little as 1 microsecond in each state (on or off). Power cycling can occur due to system glitches resulting from noise or mechanical system problems. It is important that during a power off or power down, the associated problematic latent voltages are eliminated.
Therefore, it would be desirable to provide a way to short power and ground planes on computer boards to the same potential, i.e., power-on-zero volts (POZ), so power-on-reset (POR) will work correctly.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a power-ground shorting circuit. In a first aspect of the present invention, a circuit senses when a computer board powers down and then shorts the power and ground planes together to remove latent voltage on the voltage or power plane relative to the ground plane with a controlled short time period and delay to activation time period. This allows the elimination of spurious voltage levels that might damage circuitry.
The present invention relates to a circuit for powering down a power line or plane, comprising a comparator for comparing the voltage on the power line with an internal reference voltage to provide a comparator output signal, a delay circuit receiving the comparator output signal and generating a delay circuit output signal, a booster circuit for providing a booster circuit output signal greater in magnitude than the magnitude of the delay circuit output signal if needed to activate the switching circuit; and a switching circuit which is activated by the booster circuit output signal so as to eliminate latent voltages on the power line or plane.
The present invention relates to a method of shorting a power bus line or plane to ground, comprising the steps of comparing an internal reference voltage with the power bus line voltage, generating a power fault signal if the difference between the internal reference voltage and the power bus line voltage exceeds a threshold, generating a time delay signal as a result of the power fault signal, generating a signal as a result of the time delay signal, and activating a switch to drive the power bus line to ground.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5432386 (1995-07-01), Cerra et al.
patent: 5883501 (1999-03-01), Arakawa
patent: 6151529 (2000-11-01), Batko
patent: 6329851 (2001-12-01), Murphy
Lair Donald M
Le N.
LSI Logic Corporation
Suiter & Associates PC
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