Power/ground configuration for low impedance integrated circuit

Details Power/ground configuration for low impedance integrated circuit Power/ground configuration for low impedance integrated circuit

2002-07-31

2004-08-31

Thai, Luan (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S668000, C257S692000

Reexamination Certificate

active

06784532

ABSTRACT:

TECHNICAL FIELD
An integrated circuit that includes a low impedance current path to supply power to a die, and more particularly, to an integrated circuit with an interlocking power/ground configuration.
BACKGROUND
The current paths in integrated circuits must be able to handle ever-increasing current levels which are being used to power such devices as processors and application-specific integrated circuits (ASICs). Processors need more power in order to operate at multiple-gigahertz frequencies and to simultaneously perform numerous logic and memory operations. Resistance along the current paths at higher current levels often generates enough heat to damage the processor.
Higher currents also generate more inductance along the current paths to the processor. The higher inductance can increase the impedance in the current paths until the high impedance degrades signals that are sent to the processor.
Current is typically supplied to a processor through a plurality of pins. One way to deal with the concerns created by supplying high currents is to add more pins, because a greater number of pins will have a larger cumulative cross-sectional area resulting in a lower resistance.
The drawbacks with adding pins include increased cost and the use of precious space on the integrated circuit. In addition, when pins are added they may not have a significantly lowered resistance as compared to the resistance of the pins in the more active regions of the processor. Therefore, the additional pins may not be effective in reducing current through certain regions of the integrated circuit.
There is a need for an integrated circuit that includes a low impedance current path that is parallel to existing pins such that some current is delivered through the low impedance parallel path instead of through the pins. Reducing the amount of current through the pins decreases the heat that is generated by the pins during operation of the die.


REFERENCES:
patent: 6274925 (2001-08-01), Fazelpour
patent: 6326678 (2001-12-01), Karnezos et al.
patent: 6424032 (2002-07-01), Ikemoto et al.

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