Power, ground and decoupling structure for chip carriers

Details Power, ground and decoupling structure for chip carriers Power, ground and decoupling structure for chip carriers

1981-08-14

1983-10-18

James, Andrew J.

Stock material or miscellaneous articles

Composite

Of bituminous or tarry residue

357 70, 357 68, 29576R, 29589, 428620, H01L 3902, H01L 2348, H01L 2944

Patent

active

044109059

ABSTRACT:
A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.

REFERENCES:
patent: 3648122 (1972-03-01), Berglund et al.
patent: 4366342 (1982-12-01), Breedlove

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