Power grid layout techniques on integrated circuits

Details Power grid layout techniques on integrated circuits Power grid layout techniques on integrated circuits

2005-09-27

2008-12-09

Parker, Kenneth (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257SE23020, C257S738000, C257S780000, C257S784000, C257S786000, C438S612000, C174S255000, C174S262000

Reexamination Certificate

active

07462941

ABSTRACT:
Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDDand a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

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