Power grid and bump pattern with reduced inductance and...

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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C361S774000

Reexamination Certificate

active

06961247

ABSTRACT:
Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.

REFERENCES:
patent: 6160298 (2000-12-01), Ohkubo
patent: 6305000 (2001-10-01), Phan et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 6410990 (2002-06-01), Taylor et al.
patent: 6483714 (2002-11-01), Kabumoto et al.

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