Static information storage and retrieval – Powering
Reexamination Certificate
2002-06-14
2003-12-23
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
C365S222000, C365S236000, C365S189070
Reexamination Certificate
active
06667929
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and apparatus for limiting the power consumption of a computer processor, dynamic random access memory (DRAM) subsystem, and more particularly, to a method and apparatus that is relatively simple to implement with existing DRAM subsystems.
BACKGROUND
Technical issues, such as a need for cooling and a small physical size, place a restriction on the amount of power available in a computer system. At the same time, a demand for increased computer performance pushes up memory size and operating frequency and this, in turn, requires additional power from the system power supply.
A number of proposals have been made in the prior art to limit the power consumption of computer processors, including inhibiting access to one port of a dual ported RAM. In general these prior art proposals are based upon decreasing power for a function where the need for the function decreases.
SUMMARY OF THE INVENTION
An object of this invention is the provision of a method and apparatus to limit the average power consumption of a DRAM subsystem in a computer processor by indirectly measuring actual power consumption and decreasing the power consumption when the consumption exceeds a preset amount.
Another object is the provision of a system that is easy to implement with existing DRAM subsystems, and that has a small impact on DRAM subsystem operation.
Briefly, this invention contemplates the provision of a method and apparatus to limit the average power consumption of a DRAM memory subsystem by determining the number of memory transfers in a sample interval and reducing the maximum transfer rate if the number exceeds a predetermined value. In a specific embodiment, the system counts the number of memory transfers requested in a sample interval, which preferably is defined as the interval between the DRAM refresh cycles. If the count exceeds a predetermined number, the system increases the minimum interval between memory transfer requests in succeeding sample intervals until the count in a succeeding sample interval is below another lower predetermined number. The system then reestablishes the minimum interval between transfers to the interval dictated by parameters established by the memory subsystem uninhibited by the power consumption limiting system of this invention.
REFERENCES:
patent: 5734919 (1998-03-01), Walsh et al.
patent: 5844849 (1998-12-01), Furutani
patent: 5926435 (1999-07-01), Park et al.
patent: 5996083 (1999-11-01), Gupta et al.
patent: 6038673 (2000-03-01), Benn et al.
patent: 6141278 (2000-10-01), Nagase
patent: 6459621 (2002-10-01), Kawahara et al.
Chin Henry
Shen William W.
Zaharinova-Papazova Vesselina K.
Augspurger Lynn L.
Lebentritt Michael S.
Marhoefer Laurence J.
Nguyen Tuan T.
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