Electrical transmission or interconnection systems – Plural load circuit systems – Selectively connected or controlled load circuits
Reexamination Certificate
2011-01-11
2011-01-11
Kaplan, Hal I. (Department: 2836)
Electrical transmission or interconnection systems
Plural load circuit systems
Selectively connected or controlled load circuits
C307S038000
Reexamination Certificate
active
07868479
ABSTRACT:
Circuitry for implementation of power gating within a multimedia processing environment is described. The disclosed circuitry supports effective power management for a multimedia display processor, which may include various components that operate separately from one another. In this manner, the disclosed circuitry can support power conservation and enhanced performance within a multimedia processing environment. In some aspects, headswitch or footswitch circuitry may be implemented to selectively connect and disconnect different logic components of a multimedia display processor to a power rail depending on the operating mode of the respective logic component, e.g., depending on whether the logic component is in an active or inactive mode.
REFERENCES:
patent: 5615162 (1997-03-01), Houston
patent: 5926034 (1999-07-01), Seyyedy
patent: 6516447 (2003-02-01), Wadland et al.
patent: 6518826 (2003-02-01), Zhang
patent: 6639454 (2003-10-01), Hoshi et al.
patent: 6653693 (2003-11-01), Makino
patent: 6900478 (2005-05-01), Miyagi
patent: 7076681 (2006-07-01), Bose et al.
patent: 2002/0191104 (2002-12-01), Matsutani et al.
patent: 2003/0094661 (2003-05-01), Miyagi
patent: 2003/0112042 (2003-06-01), Takahashi
patent: 2003/0218478 (2003-11-01), Sani et al.
patent: 2004/0026751 (2004-02-01), Makino
patent: 2005/0276132 (2005-12-01), Severson et al.
patent: 2006/0206737 (2006-09-01), Lee
patent: 2006/0270427 (2006-11-01), Shida et al.
patent: 2006/0282826 (2006-12-01), Dockser
patent: 2009/0137221 (2009-05-01), Nanda et al.
Benton H. Calhoun et al., “Design methodology for fine-grained leakage control in MTCMOS” Proceedings of the 2003 International Symposium on Low Power Electronics and Design, ISLPED'03. Seoul, Korea, Aug. 25-27, 2003; [International Symposium on Low Power Elctronics and Design], 20030825; 20030825-20030827 New York, NY: ACM, US pp. 104-109 XP010658596.
International Search Report and Written Opinion—PCT/US2008/067985, International Search Authority— European Patent Office—Dec. 7, 2009.
Gambale, Jr. James R.
Kaplan Hal I.
Qualcomm Incorporated
LandOfFree
Power gating for multimedia processing power management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power gating for multimedia processing power management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power gating for multimedia processing power management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2741913