Power field effect devices having low gate sheet resistance and

Details Power field effect devices having low gate sheet resistance and Power field effect devices having low gate sheet resistance and

1989-06-01

1991-01-15

Hille, Rolf

357 41, 357 59, 357 65, H01L 29100, H01L 27020, H01L 29780, H01L 29040

Patent

active

049857401

ABSTRACT:
A multi-cellular power field effect semiconductor device includes a tungsten silicide/polysilicon/oxide gate electrode stack with low sheet resistance. Preferably, a layer of tungsten is also disposed in intimate contact with the source region of the device. This tunsten layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this tungsten layer greatly reduces the resulting ohmic contact resistance to the region. If desired, a tunsten layer can also be disposed in contact with the drain region of the device, again, to lower ohmic contact resistance. The device has substantially improved operating characteristics. Novel processes for producing the device are also described.

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K. Shenai, et al., "Characteristics of As-Deposited and Sintered Mo/LPCVD W Contacts to As, B, and P Doped Silicon", Proceedings of the 1987 Workshop on Tungsten and Other Refractory Metals for VLSI Applications III, Materials Research Society, 1988, pp. 219-226.

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