Power FET with gate segments covering drain regions disposed in

Details Power FET with gate segments covering drain regions disposed in Power FET with gate segments covering drain regions disposed in

1992-01-21

1994-06-21

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257331, 257341, 257401, H01L 2910, H01L 2978, H01L 2710

Patent

active

053230361

ABSTRACT:
In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.

REFERENCES:
patent: 4015278 (1978-03-01), Fukuta
patent: 4055884 (1977-11-01), Jambotkar
patent: 4072975 (1978-02-01), Ishitani
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4412242 (1983-10-01), Herman et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4823176 (1989-04-01), Baliga et al.
patent: 4974059 (1990-11-01), Kinzer
patent: 4982249 (1991-01-01), Kim et al.
patent: 5008725 (1991-04-01), Lidow et al.
patent: 5008725 (1991-04-01), Lidow et al.
patent: 5192989 (1993-03-01), Matsushita et al.
"High Efficiency Power Switching with Cascaded Hxfets and Bipolars," Electronic Engineering, Nov. 1981, p. 61.

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