Electricity: power supply or regulation systems – In shunt with source or load – Using choke and switch across source
Reexamination Certificate
1999-05-26
2001-01-16
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using choke and switch across source
C363S081000, C363S089000
Reexamination Certificate
active
06175218
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a power factor correction (PFC) controller. More specifically, the present invention relates to a boundary mode PFC controller using a boost converter.
(b) Description of the Related Art
FIG. 1
shows a schematic of conventional boundary mode PFC controller using a boost converter, comprised of a boost converter
10
and a switching controller
20
. The boost converter
10
rectifies input AC power and generates rectified power voltage Vs, and outputs a voltage Vout to a load part according to the operation of a switch (a metal oxide semiconductor field effect transistor or MOSFET). The switching controller
20
controls the switch of the boost converter
10
. The switching controller
20
detects a fluctuation of input voltage or output voltage and controls the switch, such that the output voltage of the boost converter
20
is regulated to a specified value.
Referring to
FIG. 1
, when input voltage is assumed to be increased, the voltage Vm1, divided from the voltage Vs by the resistors R
3
and R
4
, is increased, and accordingly, the output voltage Vmo of a multiplier
23
is also increased. Therefore, the point at which the voltages Vmo and Vcs provided to a comparator becomes equal is delayed, and hence the ON interval of the switch is increased. Hence, the output voltage Vout of the boost converter
10
is increased.
When the output voltage Vout of the boost converter
10
is increased, output voltage Vm2 of the error amplifier
21
is reduced, and an output voltage Vm2−Vref of subtracter
21
is reduced. Hence, the output voltage Vmo of the multiplier is reduced.
In the boundary mode PFC controller, when the input voltage is increased, the multiplier output voltage Vmo is momentarily increased, but the subtracter output voltage Vm2−Vref provided to the multiplier
23
is reduced due to the increase in the boost converter
10
output voltage, and the multiplier output voltage Vmo is reduced. Therefore, the multiplier output voltage Vmo continues to be constant, independent of the increase in input voltage, and the boost converter
10
output voltage Vout is regulated.
That is, as shown in
FIG. 2
, when the input voltage is increased and the voltage Vm1 is increased to Vm1′, the output voltage Vm2 of the error amplifier
21
is reduced to Vm2′, and eventually, the output voltage Vmo of the multiplier
23
is maintained to be constant.
However, in the prior art boundary mode PFC controller, when the input voltage is highly increased more than a specified voltage, the output voltage Vm2 of the error amplifier is increased to be higher than the reference voltage Vref, and the output voltage of boost converter
10
is no longer regulated. That is, in the prior art, the fluctuation range of the input voltage is limited by the reference voltage Vref.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a boundary mode PFC controller having a minimal limitation in the fluctuation range of the input voltage.
In one aspect of the present invention, the PFC controller comprises a converter, an error amplification unit, a calculator, a comparator, a zero current detection unit, and a switching driver.
The converter comprises a transformer coupling the primary coil to input voltage, a switch controlling the current flowing to the primary coil, and a first diode and a first capacitor rectifying the output voltage of the primary coil and supplying the rectified voltage to the load. The first diode, the first capacitor, and the switch configure a boost converter, and the switch is a MOSFET. The converter may further comprise a second diode coupled to one end of the second coil of the transformer, and a first resistor and a second capacitor coupled in series to between the second diode and the ground.
The error amplification unit comprises an error amplifier amplifying the difference between a voltage proportional to the output voltage of the converter and a first reference voltage, and a subtracter subtracting the output voltage of the error amplifier from a second reference voltage. The first reference voltage may be equal to second reference voltage.
The calculator receives a first and a second input voltages proportional to the input voltage of the converter and receiving the output voltage of the subtracter as inputs, and outputs the voltage proportional to the first input voltage and the output voltage of the subtracter and inversely proportional to the second input voltage. The first input voltage may be obtained by dividing the input voltage of the converter by the second and third resistors, and the second input voltage is obtained by dividing the voltage charged in the second capacitor by a specific value.
The comparator compares the voltage which detects the current flowing to the switch with the output voltage of the calculator. The zero current detection unit comprises a zero current detector comparing the voltage of the back electromotive force of the secondary coil of the transformer with a third reference voltage and detecting the zero current of the coil. The zero current detection unit may further comprise a clamping circuit clamping the back electromotive force voltage of the secondary coil of the transformer.
The switching driver controls the switch to OFF when the output voltage of the calculator becomes equal to the voltage which detects the current flowing to the switch, and controls the switch to ON when the switching driver detects the zero current of the secondary coil of the transformer. The switching driver may be comprised of: an R-S latch circuit, receiving the output voltage of the comparator through the reset terminal, and receiving the inverted output voltage of the zero current detector through the set terminal; a logical NOR gate, receiving the output voltage of the zero current detector and the output voltage of the R-S latch circuit; and a driver, controlling the switch to ON and OFF according to the output signal of the logical NOR gate.
REFERENCES:
patent: 5359281 (1994-10-01), Barrow et al.
Choi Nak-choon
Jang Kyung-hee
Seo Maeng-ho
Blakely & Sokoloff, Taylor & Zafman
Fairchild Korea Semiconductor Ltd.
Patel Pajnikant B
Wong Peter S.
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