Power factor correction circuit

Electric power conversion systems – Current conversion – With condition responsive means to control the output...

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323222, 363 81, 363 89, H02M 7217

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active

050069756

ABSTRACT:
A power factor correction circuit in which a divided-down version of a rectified input waveform is sampled approximately at its peak by a sample-and-hold circuit. The peak value is then processed to produce a correction signal which is subtracted from the original divided down rectified signal. This produces a reference signal which is then multiplied by the output of an error amplifier to produce a sinusoidal reference signal for the input current. The output of the error amplifier which is used is that which is sampled periodically when the divided-down rectified signal approaches zero volts. The sinusoidal reference is used by peak and valley comparators whose other inputs come from a current sense amplifier. The outputs of the comparators are used to switch a shunting transistor which controls the input current to achieve near unit y power factor.

REFERENCES:
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patent: 4437146 (1984-03-01), Carpenter
patent: 4472672 (1984-09-01), Patcholok
patent: 4529927 (1985-07-01), O'Sullivan et al.
patent: 4683529 (1987-07-01), Bucher
patent: 4816982 (1989-03-01), Severinsky
patent: 4819122 (1989-04-01), Gontowski, Jr.
patent: 4825351 (1989-04-01), Vesugi
Redl et al, "Switching Mode Power Converters: . . . ," POWERCON 7, pp. 1-16, Mar. 25-27, 1980.
Szepesi, "Stabilizing the Frequency of Hysteretic Current-Mode DC/DC Converters," IEEE Trans. on Pwr. Elect., vol. PE-2, No. 4, pp. 302-313, Oct. 1987.
Neufeld, Herman, "Control IC for Near Unity Power Factor in SMPS", published in the Power Conversion and Intelligent Motion Control Conference (PCIM), dated Oct. 16, 1989.

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