Power electronic module packaging

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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Details

C257S712000, C257S717000

Reexamination Certificate

active

06232151

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to electronic packaging technology and, more particularly, to electronic packaging technology applicable to power modules, such as ac-ac, ac-dc and dc-ac converters and electronic switches.
Typical power module designs employ wire bonds for connecting power devices to power busses and control terminals. The power devices are commonly soldered onto a metalized insulating ceramic substrate, often beryllium oxide or aluminum nitride metalized with a conductive metal such as copper or aluminum, and subsequently bonded to a massive copper heat spreader. Typically, an injection molded polymer shell covers the module, exposing only the input/output and control terminals and the copper heat spreader. The heat spreader is attached to a heat sink, such as extruded aluminum fins or a cold plate, for example. Thermal contact between the heat spreader and the heat sink is achieved through a thermal paste or a thermally conductive polymer.
Disadvantages of presently available power module designs such as those described hereinabove include relatively high parasitic impedance, high volume and weight, high thermal resistance, and limited reliability primarily due to wire bonds. Accordingly, it would be desirable to provide power electronic module packaging technology that overcomes such disadvantages.
BRIEF SUMMARY OF THE INVENTION
In accordance with preferred embodiments of the present invention, a method of power electronic packaging comprises a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. The method comprises attaching a planar single- or multi-layer membrane structure to a carrier frame and forming a via pattern in the membrane. The single-layer structure comprises a flexible organic dielectric film; and the multi-layer structure comprises a flexible organic dielectric film bonded to a metal sheet. Either the multi-layer or single-layer structure is coated with a glue layer that is protected by a release sheet. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure may comprise different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.


REFERENCES:
patent: 5353195 (1994-10-01), Fillion et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5532512 (1996-07-01), Fillion et al.
patent: 5561321 (1996-10-01), Hirano
patent: 5570502 (1996-11-01), Sawtell
patent: 5637922 (1997-06-01), Fillion et al.
patent: 5841193 (1998-11-01), Eichelberger
“Power Overlay Chip Scale Packages for Discrete Power Devices,” Fillion et al. Ser. No. 09/255,412, filed Feb. 22, 1999.

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