Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2006-04-11
2006-04-11
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S207000, C365S221000, C365S240000
Reexamination Certificate
active
07027348
ABSTRACT:
An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j<k) for a time period sufficient to sense the signal on a connected column line associated with each of the plurality (j) of sense amplifiers. The control circuit latches the signal into the register; and deactivates the first plurality (j) of sense amplifiers; and serially outputs the signal from the register in response to the clock signal.
REFERENCES:
patent: 3930239 (1975-12-01), Salters et al.
patent: 4747081 (1988-05-01), Heilveil et al.
patent: 4914630 (1990-04-01), Fujishima et al.
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5222047 (1993-06-01), Matsuda et al.
patent: 5663922 (1997-09-01), Tailliet
patent: 5666324 (1997-09-01), Kosugi et al.
patent: 5959900 (1999-09-01), Matsuda
patent: 6018794 (2000-01-01), Kilpatrick
patent: 6097657 (2000-08-01), Ng et al.
patent: 6134178 (2000-10-01), Yamazaki et al.
patent: 6587374 (2003-07-01), Takagi et al.
Berger Neal
Chang George Chia-Jung
Cheng Pearl Po-Yee
Koh Anne Pao-Ling
DLA Piper Rudnick Gray Cary US LLP
Nguyen Tan T.
Silicon Storage Technology, Inc.
LandOfFree
Power efficient read circuit for a serial output memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power efficient read circuit for a serial output memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power efficient read circuit for a serial output memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3599242