Power efficient integrated charge pump using clock gating

Details Power efficient integrated charge pump using clock gating Power efficient integrated charge pump using clock gating

2004-02-13

2004-10-05

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C363S059000

Reexamination Certificate

active

06801078

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to reducing current consumption in voltage multiplier circuits used for programmable memories, and more particularly to an integrated circuit including an oscillator for generating a clock signal, a charge pump circuit controlled on the basis of the clock signal in order to generate a high voltage for programming memories and a regulation feedback loop for controlling the high voltage level. The feedback loop includes a feedback circuit connected to the output of the charge pump circuit and a means for gating the clock signal, which is disposed in the feedback loop between the oscillator and the charge pump circuit, the means being controlled by a gating signal supplied by the feedback circuit. The feedback circuit comprises means for generating, on the basis of the high output voltage, an intermediate control voltage which varies within a determined voltage range defined by minimum and maximum voltage levels.
DESCRIPTION OF THE RELATED ART
In the prior art, as illustrated in
FIG. 1
, the document U.S. Pat. No. 6,157,243 discloses a high voltage generation circuit including an oscillator
1
that outputs two clock signals Phi and Phib in phase opposition that are used by a charge pump circuit
2
. This charge pump circuit
2
outputs a high voltage HV. This high voltage is used by circuitry
4
for programming or erasing a non-volatile memory. This high voltage HV is also supplied to a regulation circuit
3
that outputs a control signal Run. This control signal Run is supplied to an enabling input En of the oscillator
1
.
The oscillator has a stage
5
for generating a clock signal CLK. The output S
1
of this stage
5
is looped to its input E
1
through a NAND-type logic gate
6
. At another input this logic gate
6
receives the control signal Run that is supplied to the enabling input En of the oscillator
1
. The output of the logic gate
6
that is relied to the input E
1
of the stage
5
supplies a first inverter
7
followed in series with a second inverter
8
that outputs of said inverters deliver the two clock signals Phi and Phib in phase opposition.
The regulation circuit
3
includes a Zener diode
9
and a resistor
10
series-connected between the high output voltage HV of the charge pump circuit
2
and ground. An inverter
11
, whose input is connected to a connection point P between the diode
9
and the resistor
10
, outputs the control signal Run. The Zener diode
9
has a Zener voltage equal to 18 Volts. It is the Zener voltage which gives the reference voltage level Vref for the regulation circuit
3
.
When the high voltage HV exceeds this reference voltage Vref of 18 Volts, the current in the diode
9
increases and the voltage at the connection point P tends to rise. At the output of the inverter
11
of the regulation circuit
3
, the control signal Run therefore goes to 0. This deactivates the oscillator
1
. This deactivation corresponds to the freezing of the clock signals Phi and Phib, which remain in a given state. The charge pump circuit
2
therefore no longer operates. The level of the output voltage HV will then gradually fall, either because of current leakages or because of the activation of a circuit
4
for programming the memory.
When the high voltage HV is lower than the reference voltage Vref, the current in the arm of the regulation circuit
3
is very low and the voltage at the connection point P is close to zero. The control signal Run then goes to 1. This activates the oscillator, and the output level of the charge pump circuit
2
will rise again. This type of regulation of the charge pump circuit is called the “go-no-go” mode of regulation.
The solution according to U.S. Pat. No. 6,157,243 presents some drawbacks. The control signal Run is directly determined by the comparison between the output voltage HV and the reference voltage Vref. Therefore, when the output voltage is close to the reference voltage, the high voltage generation circuit oscillates due to the constant activation and deactivation of the oscillator
1
and consequently of the charge pump circuit
2
. This results in an increased power consumption and in increase of the noises, such as supply and ground noises. Further, the activation and deactivation of the oscillator
1
introduces transition clock modes that can affect the efficiency of the charge pump circuit
2
.
In another prior art, as illustrated in
FIG. 2
, the document EP 0 655 827 also discloses a high voltage generation circuit comprising a classical charge pump circuit
21
, a clamp circuit
22
, a voltage detecting circuit
23
and a clock control circuit
24
.
The clamp circuit includes a PMOS transistor
25
having its gate connected to the supply voltage Vdd and its source electrode connected to the high output voltage HV, and an NMOS transistor
26
having its drain connected to the drain of the PMOS
25
, its gate connected to the supply voltage Vdd and its source electrode connected to ground.
The voltage detecting circuit
23
is composed of an inverter
27
having an input connected to a connection node B between the PMOS
25
and the NMOS
26
transistors.
The clock control circuit
24
has a NAND gate
28
having one input connected to an external clock, e.g. an oscillator
29
, and the other input connected to an output line D of the inverter
27
. An output of the NAND gate
28
is connected to the clock input terminal of the charge pump circuit
21
.
The above described circuit works as follows. When a pump-up operation is started, since the high output voltage HV is lower than a predetermined regulation voltage, the PMOS
25
in the clamp circuit
22
is off, and therefore, the node B is pulled down by the NMOS
26
. Since a voltage VB on the node B is at a low level, the output D of the inverter
27
is at a high level, and therefore, the clock signal supplied to the external clock is supplied through the NAND gate
28
to the clock input terminal as an internal clock. Thus, the charge pump circuit
21
is put into operation, so that the electric charge is supplied to the high output voltage, and therefore, the high output voltage is rising up.
When the high output voltage HV reaches a clamp voltage Vcl (=Vdd+Vtp), where Vtp is the threshold voltage of the PMOS
25
, the PMOS is turned on so that the potential VB on the node B is brought to a high level. Accordingly, the potential on the output line D of the inverter
27
becomes the low level (which constitutes a detection signal), and the output of the NAND gate
28
is brought to a high level.
Accordingly, the clock signal supplied to the external clock is not transmitted to the clock input terminal, and therefore, the charge pump circuit
21
stops its operation.
Incidentally, in the high voltage generating circuit, when the voltage elevation is completed and therefore when the charge pump circuit
21
is stopped, the elevation of the high output voltage HV stops in a first time and decreases after, so the PMOS
25
is turned off. Therefore, the potential VB on the node B is pulled down by the NMOS
26
and drops below a logical threshold level of the inverter
27
.
Accordingly, the potential of the output of the line D of the inverter
27
is brought to the high level, so that the clock signal is supplied through the NAND gate
28
to the clock input terminal, and therefore, the charge pump circuit
21
starts its pumping-up operation again. As a result, the high output voltage HV elevates to the clamp voltage Vcl, and the voltage detection signal D is outputted again so as to stop the pumping-up operation of the charge pump circuit
21
. These operations are repeated during each voltage elevation period.
The solution according to EP 0 655 827 also presents some drawbacks. The potential of the output of the line D of the inverter
27
controls the activation and deactivation of the charge pump circuit
21
. The deactivation signal depends directly on the comparison between the high output voltage HV and the reference voltage, that corresponds to th

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