Power efficient booth multiplier using clock gating

Details Power efficient booth multiplier using clock gating Power efficient booth multiplier using clock gating

1995-08-31

1997-08-26

Gordon, Paul P.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

056616732

ABSTRACT:
A multiplier which uses Booth recoding to multiply large word length operands. The multiplier can be divided into three functional modules: 1) operand loading module, 2) Booth partial product calculation and accumulation module, and 3) accumulator shift function module which builds the final 512 bit product. Each of the three stages is clocked independently of the others. The clock signals used to control the data processing operations and flow of data through the registers and adders are gated so that those registers which are needed for the stage of the multiplication operation being executed are clocked, while the other registers are not enabled.

REFERENCES:
patent: 4048621 (1977-09-01), Conklin et al.
patent: 4615005 (1986-09-01), Maejima et al.
patent: 4876598 (1989-10-01), Carlstedt et al.
patent: 4876660 (1989-10-01), Owen et al.
patent: 5325049 (1994-06-01), Hayashi et al.
patent: 5392437 (1995-02-01), Matter et al.
patent: 5410683 (1995-04-01), Al-Khairi
patent: 5420808 (1995-05-01), Alexander et al.
patent: 5433541 (1995-07-01), Hieda et al.
patent: 5436860 (1995-07-01), Shankar et al.
patent: 5502689 (1996-03-01), Peterson et al.
Koren, Israel, "High-Speed Multiplication", Computer Arithmetic Algorithms, Chapter 6, pp. 99-106, Prentice Hall, Inc., 1993.
Short, Kenneth L., Microprocessors, Microprocessors and Programmed Logic, Second Edition, pp. 241-243, Prentice-Hall, Inc., 1987.
Taylor, Fred J., Digital Filter Design Handbook, pp. 578-581, Marcel Dekker, Inc., 1983.
Rabiner, Lawrence R. & Gold, Bernard, Theory And Application of Digital Signal Processing, pp. 514-524, Prentice-Hall, Inc., 1975.
Ohkubo, Norio et al., "A 4.4 ns CMOS 54.times.54-b Multiplier Using Pass-Transistor Multiplexer", IEEE Journal of Solid-State Circuits, vol. 30, No. 3, pp. 251-257, Mar. 1995.
Omondi, Amos R., Computer Arithmetic Systems, Algorithms, Architecture and Implementations, pp. 152 & 154, Prentice-Hall, 1994.
Patterson, David A., "Compputer Arithmetic", Computer Architecture A Quantitative Approach, pp. A-1 thru A-10 & A-39 thru A-44, Morgan Kaufmann Publishers, Inc., 1990.

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