Power down system for regulated internal voltage supply in DRAM

Details Power down system for regulated internal voltage supply in DRAM Power down system for regulated internal voltage supply in DRAM

2000-02-21

2001-06-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S222000, C365S233100, C365S226000

Reexamination Certificate

active

06249473

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a circuitry for a Dynamic Random Access Memory (DRAM), and more particularly to a power down system for regulated internal voltage supply in DRAM.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) employs capacitors of its memory cells to reserve charges by external power supply. As a result of the improvement of Very Large Scale Integrated circuits (VLSI) technology, the memory density is moving toward a higher capacity, thus multiplying the number of memory cells. Those multiplied memory cells consume a great amount of power supply, but the power specification of the printed circuit board, on which the DRAM is mounted, has remained the same or has even been reduced over the past decades. Therefore, while the number of memory cells and memory density have greatly increased, the internal power consumption has become a vital issue for DRAMs.
For overcoming the disadvantage of high power consumption of the DRAM, a traditional power down scheme is employed to turn off a regulator to cut off internal power supply of the DRAM for saving, on power consumption. When the DRAM enters the power down state, a power down signal responsive to a clock enable signal, which would suspend an internal clock of DRAM, turns off the regulator, thereby stopping the internal power supply for the peripheral circuits and memory banks of the DRAM.
In designing the power down scheme, it is important to carefully consider the relation between the clock enabling signal and ACT command, which is employed to turn on the gates along a selected word line. Since the ACT command takes a period to completely turn on the gates of selected word line, when the clock enable signal follows the ACT command immediately, it would suspend the internal clock, thereby risking the information read or written by the ACT command under incompletion.
In addition, the control of self-refresh clock is also an important concern whiling designing the power down scheme. The self-refresh clock is a normally stable signal. When the self-refresh clock enters the self-refresh mode, it would toggle at a specific frequency to inform the control circuit of the DRAM to refresh its memory cells. Meanwhile, the internal power supply is not available to be cut off due to the proceeding refresh mode. Since the power down scheme could only be activated under a non-refresh mode, correctly detecting the self-refresh clock's waveform for making sure the refresh state turns out to be a key issue for designing power schemes.
As illustrated above, only if the ACT command is completed and the non-refresh mode is detected, the power down scheme would turn off the regulator to decrease the power consumption of the DRAM. Under this understanding, this power down system is proposed to meet the above criteria to save power consumption of the DRAM.
SUMMARY OF THE INVENTION
An object of the invention is to provide a power down system, which comprises a plurality of logic devices, for regulating power supply in a DRAM. The power down system generates a power down signal according to a scheme, which turns off a regulator in the DRAM, only if an ACT command is completed and a waveform of a self-refresh clock is correctly detected.
This invention discloses a power down system for regulated internal power supply in the DRAM, which comprises a RAS control module, self-refresh clock control circuit, and a power down control circuit. The RAS control module responds with row address strobe signals of corresponding memory banks to output a first power down control signal. The row address strobe signals denote whether the memory banks are at active states. While all the row address strobe signals are in a first condition of inactivity, the first power down control signal will inform the power down system to turn off a regulator in the DRAM under the first condition. The self-refresh clock control circuit responds with a self-refresh clock to output a second power down control signal. While the self-refresh clock is in a second condition of non-self-refresh mode, the second power down control signal will inform the power down system to turn off the regulator under the second condition. The power down control circuit coupling with the ras control module and self-refresh clock control circuit receives an input clock enable signal, the first power down control signal, and the third power down control signal to output a power down signal to turn off the regulator for saving power consumption. Since the power down system can only be triggered under the above two conditions, the affection of ACT command and confusion of refresh mode would be avoided.


REFERENCES:
patent: 6058063 (2000-05-01), Jang

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