Power down sequence for electrically programmable memory

Details Power down sequence for electrically programmable memory Power down sequence for electrically programmable memory

1980-02-04

1982-02-02

Konick, Bernard

Static information storage and retrieval

Powering

Conservation of power

365205, G11C 700

Patent

active

043143628

ABSTRACT:
An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. A power down mode of operation is provided in which current flow in various circuits of the device is greatly reduced. To speed up access time in exiting from power down, the reference voltage input to the sense amplifier is shifted during power down then when exiting returns to its operating value according to a time constant.

REFERENCES:
patent: 4069474 (1978-01-01), Boettcher et al.
patent: 4122547 (1978-10-01), Schroeder et al.
patent: 4158241 (1979-06-01), Takemae et al.
patent: 4181865 (1980-01-01), Kohyama
patent: 4195357 (1980-03-01), Kuo et al.

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