Power-down circuits for dynamic MOS integrated circuits

Details Power-down circuits for dynamic MOS integrated circuits Power-down circuits for dynamic MOS integrated circuits

1985-03-18

1987-08-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 307480, 307453, 365227, 365228, 328 72, G06F 104, H03K 513

Patent

active

046863869

ABSTRACT:
A power-down circuit for saving operational power dissipation of a dynamic MOS integrated circuit during idling conditions. A clock divider generates a divided clock signal in response to an internal clock signal inputted thereto. The divided signal is synchronized with the internal clock signal and has a repetition rate which is slower than that of the internal clock signal. A control circuit delivers the control signal when a triggering signal is inputted thereto. A clock selecting circuit transfers either the internal clock signal or the divided clock signal to the dynamic MOS integrated circuit in response to the control signal.

REFERENCES:
patent: 4137563 (1979-01-01), Tsunoda
patent: 4293927 (1981-10-01), Hoshii
patent: 4317180 (1982-02-01), Lies

Affiliated with

Also associated with

Rating

Power-down circuits for dynamic MOS integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power-down circuits for dynamic MOS integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power-down circuits for dynamic MOS integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-404116