Power down circuit for testing memory arrays

Static information storage and retrieval – Powering – Data preservation

Patent

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Details

365201, 365200, 365185, G11C 1140

Patent

active

053134303

ABSTRACT:
A power down circuit for a default detection circuit, for detecting defects in memory array cells, comprising means for diverting the memory array standby current around the memory array cells to achieve the maximum ratio of change in input voltage as compared to the change in cell standby current and to provide improved tracking of the memory array over statistical variations of temperature, power supplies, process and other variables.

REFERENCES:
patent: 4553225 (1985-11-01), Ohe

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