Power distribution system built-in self test using on-chip...

Details Power distribution system built-in self test using on-chip... Power distribution system built-in self test using on-chip...

2006-11-21

2006-11-21

Hollington, Jermele (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07138815

ABSTRACT:
A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

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patent: 6768952 (2004-07-01), Kantorovich et al.
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patent: 2001 085622 (2001-03-01), None
Isaac Kantorovich et al.; “Measurement of Milliohms of Impedance at Hundred MHz on Chip Power Slupply Loop”; Copyright 2002 IEEE; EPEP Proceedings; pp. 319-322.

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