Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-02-06
2003-10-21
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S685000, C257S686000, C257S723000, C257S724000, C257S725000, C257S778000
Reexamination Certificate
active
06635970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to semiconductor chip design, and more specifically, to a power distribution method for chip-on-chip packaging of semiconductor chips containing very large scale integrated circuit (VLSI) circuits, such as microprocessors and associated memory.
2. Related Art
Chip-on-chip module technology has facilitated increased system density and increased operating frequency by reducing interconnection distances and increasing signal propagation speed. However, these advances, and increased density of the integrated circuits on the chips themselves, have generally increased power consumption and heat generation per unit volume of packaging. Thus heat-dissipation can be problem or design limitation in chip-on-chip modules, especially those containing very large scale integrated (VLSI) circuits.
Multi-chip packages are becoming more widely used in the semiconductor industry owing to the need to achieve higher performance, lower power dissipation, and lower chip fabrication and packaging costs. Dual-chip stack packages using Controlled Collapse Chip Connection (C4) interconnects (DCSC4), such as the package depicted in
FIG. 1A
, provide a way to provide thousands of chip-chip interconnects while also providing sufficient cooling for a less-than 10 W stack, at a relatively low cost.
FIG. 1A
is a cross-sectional view of a chip-on-chip package
1
(e.g., a Dual Chip Stack package using C4 interconnections (DCSC4) package) of the related art. The chip-on-chip package
1
includes a chip-on-chip module
10
of the related art, as disclosed in
FIG. 5
of commonly assigned U.S. Pat. No. 5,977,640 entitled Highly Integrated Chip-on-Chip Packaging, issued to Bertin, et al., and assigned to International Business Machines Corporation. Incorporated herein by reference are: commonly assigned U.S. Pat. No. 5,977,640; U.S. Ser. No. 09/105,382 entitled “Micro-flex Technology in Semiconductor Packages”, by Bertin et al; and U.S. Pat. No. 6,225,699 entitled “Chip-on-Chip Interconnections of Varied Characteristics”, by Ference et al.
The chip-on-chip module
10
comprises a master chip
30
and a slave chip
40
. The master chip
30
has an active side
31
and a backside
32
. The slave chip
40
has an active side
41
and a backside
42
. Wirebonds
28
are connected to pads
35
on active side
31
of the master chip
30
, and are connected to top side
73
of a package substrate
72
. The bottom side
74
of package substrate
72
is coupled to solder balls
76
for connecting the chip-on-chip package
1
to a structure or device (e.g., to a different level of packaging). Adhesive
71
between the backside
32
of master chip
30
and the top side
73
of package substrate
72
mechanically connects chip-on-chip module
10
to package substrate
72
. A resin dam
66
and encapsulant
64
protect the chips (i.e., master chip
30
and slave chip
40
) and impart a durability to the wirebonds
28
and chip-on-chip package
1
. Metal lid
62
enables the chip-on-chip package
1
to be compact, durable, and thermally-enhanced. Metal lid
62
can operate as a heat spreader that dissipates heat released from the chip-on-chip module
10
. The adhesive
71
, as well as any adhesive between the metal lid
62
and the backside
42
of the slave chip
40
, may have a dielectric composition.
FIG. 1B
is a cross-sectional view of the chip-on-chip module
10
of
FIG. 1A
(shown without encapsulant
64
). The chip-on-chip module
10
comprises master chip
30
and slave chip
40
, fabricated in accordance with the related art. The (smaller) slave chip
40
is shown as fabricated in silicon-on-insulator (SOI) technology bonded (face to face) to the (larger) master chip
30
fabricated in bulk CMOS technology, wherein the external GND and VDD supply connections of the chip-on-chip module
10
(via wirebonds
27
and
29
) are at the edge regions of the larger (master) chip
30
. In the bulk CMOS technology (e.g., as on master chip
30
), transistors are formed directly on the active surface
34
of a bulk semiconductor substrate (e.g., bulk semiconductor substrate
33
). In the case of a SOI chip (e.g., slave chip
40
), transistors are formed in a semiconductor layer
43
of semiconductor material (e.g., silicon) that is formed on an insulation layer
46
(e.g., SiO
X
or Al
2
O
3
) that is formed on a bulk semiconductor substrate
48
(e.g., silicon). In SOI chips of the related art, a substrate contact may be provided through the insulation layer
46
to conduct electrons between the bulk semiconductor substrate
48
and the semiconductor layer
43
, and/or between the bulk semiconductor substrate
48
and one power plane for the purpose of preventing electrostatic charge from accumulating on either side of the insulation layer
46
in such a manner as to interfere with the operation of the device
47
.
A portion of the electric power current (I) required to power the Chip-on-chip module
10
is delivered to the smaller chip (i.e., slave chip
40
) for operation of devices (e.g. CMOS transistors, inverters, etc.) on the active side
41
of the smaller chip (i.e., slave chip
40
). All the electric power current (I) is delivered to the devices
37
and
47
(e.g., semiconductor devices, indenters) on the chips in the conventional manner, e.g., through power planes (e.g.,
54
,
55
,
56
,
57
) formed in metalization layers in the back-end-of-line (BEOL) layers; e.g., BEOL layers
59
and
52
of the master chip
30
and slave chip
40
, respectively. For example, current ids provided to device
47
on the active side
41
of the smaller chip (i.e., the slave chip
40
) is delivered at supply voltage VDD through wire
29
to the edge of the larger chip (i.e., the master chip
30
) and though the VDD power plane
54
in the BEOL layer
59
of the master chip
30
, through interconnections
50
(e.g., one or more solder balls) connecting master chip
30
to slave chip
40
, then through the VDD power plane
56
in the BEOL layer
52
of the smaller chip (i.e., the slave chip
40
), through the devices (e.g., device
47
such as an inverter) of the smaller chip (i.e., the slave chip
40
), and out through the Ground (GND) power plane
57
in the BEOL layer
52
of the smaller chip (i.e., the slave chip
40
), then through the interconnections
50
(e.g., solder balls) between the master chip
30
and the slave chip
40
, then through the ground (GND) power plane
55
in the BEOL layer
59
of the master chip
30
, and then through the ground wire
27
.
Note that the VDD power planes
54
and
56
, and GND power planes
55
and
57
, especially in the slave chip
40
, are compromised by the impedance (e.g., resistance) to the portion of current that must flow through interconnections
50
(e.g., a series of C4 connections) and wires
29
as well as through the power planes of master chip
30
. Persons skilled in the art will recognize that the power planes of the master chip
30
are not as well-connected to devices (e.g., device
37
) on the active surface
34
of master chip
30
in chip-on-chip module
10
as a single C4 chip in a ceramic single-chip package would be, because the interconnections
50
to the slave chip
40
prevents access points into and prevents power plane continuity in the center region of the master chip
30
.
Advances in microprocessor chip technology have resulted in semiconductor chips comprising over a hundred million transistors running at frequencies greater than 1 Ghz, and have intense RAM memory bandwidth requirements. Two very high performance chips, such as chips containing a microprocessor and memory, can together consume power and release that energy as heat on the order of 100 watts, which can exceed the power-distribution and heat-dissipation capacity of DCSC4 designs of the related art. Future applications for compact modules, such as processors, workstations, graphics engines, speech recognition systems, network-connected game consoles, etc. will require extremely high bandwidth connections between a
Lasky Jerome B.
Nowak Edward J.
Sprogis Edmund J.
International Business Machines - Corporation
Meier Stephen D.
Schmeiser Olsen & Watts
Soward Ida M.
Steinberg William H.
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