Power distribution architecture for inkjet heater chip

Details Power distribution architecture for inkjet heater chip Power distribution architecture for inkjet heater chip

2002-09-13

2004-09-07

Mills, Gregory (Department: 1763)

Etching a substrate: processes

Forming or treating thermal ink jet article

Reexamination Certificate

active

06787050

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally directed to inkjet printers. More particularly, the invention is directed to an improved inkjet heater chip architecture wherein a single layer of metallization is used for the interconnecting circuitry.
BACKGROUND OF THE INVENTION
Due to the complexity of inkjet heater chips having active electronic circuitry, the power distribution architecture requires two or more layers of metallization (conducting layers) on the silicon substrate for providing electrical connectivity to the heating elements and driving circuitry for a printhead of an inkjet printer. Requiring multiple conductive layers adds to the cost and complexity of each heater chip, making for a more expensive heater chip. Furthermore, a dielectric layer is required between the conductive layers to prevent interaction of the conductive traces of different conductive layers. Having multiple conductive and dielectric layers requires a multiple step process adding to the cost and complexity required to manufacture a single chip.
A conventional ink jet heater chip is shown in FIG.
1
. As shown in
FIG. 1
, a portion of a prior art heater chip
1
, including an ink via
2
, and the related chip electronics illustrates the associated requirement for multiple metallization (conductor) layers. As shown, the ink via
2
is an elongate channel and typically traverses the entire length of the chip
1
. The large ink via and its placement provides ink to each of the heaters
4
on the chip
1
. To provide power to the heaters
4
, a number of metallization layers are utilized. The metallization layers include the connecting circuitry between the heaters
4
, power bond pads
6
, ground bond pads
8
and driving elements
9
. The power and ground bond pads,
6
and
8
, respectively are used to attach a tape automated bonded (TAB) circuit to the heater chip
1
to electrically connect the circuits to a printer controller.
As shown in
FIG. 1
, the ink via
2
is located between the heaters
4
and associated enabling electronics for distributing ink to the heaters
4
. Since the ink via
2
is located between the heaters
4
, power bond pads
6
and ground bond pads
8
are necessarily located on the same side of the heater chip
1
. Due to the location of the ink via
2
and the co-location of the power and ground bond pads
6
and
8
, two or more metallization layers with intermediate dielectric layers are required to connect the heater
4
between the ground bond pad
8
and power bond pad
6
. Multiple metallization layers interspersed with dielectric layers are required so that the electrical connectors connecting the ground and power bond pads
8
and
6
, respectively with the heaters
4
do not contact one another. Hence, due to this chip architecture, specifically the location of the ink via
2
, the electrical connections are necessarily in an overlapping configuration.
SUMMARY OF THE INVENTION
A need exists for a less costly and complex heater chip design. Accordingly, the invention provides a low cost single level metallization heater chip architecture. According to a preferred embodiment of the invention, a printhead heater chip is provided for use in a printhead of an inkjet printer having a printer controller. The heater chip includes a substrate having a substrate surface and a device surface opposite the substrate surface. The device surface includes a power side and a ground side, wherein the power side and the ground side are in opposing relation on the device surface of the chip. A plurality of transistor devices are also located on the device surface of the chip and separate the power and ground sides of the heater chip. Each transistor device includes a gate region, source region and drain region, and is selectively activated according to a logical input from the printer controller. A plurality of resistive heating devices are located on the device surface of the substrate and are electrically connected to the plurality of transistor devices. Each resistive heating device includes a first end and a second end and each heating device is selectively activated according to the activation of a respective transistor device. A plurality of ink vias etched through from the substrate surface to the device surface are located in a spaced apart array for providing ink from an ink reservoir adjacent the substrate surface of the chip to one or more of the resistive heating elements, wherein the ink vias are located between the transistor devices and the power side of the heater chip. The chip includes at least one ground input defined by a single layer of conductive material, wherein the ground input is located proximate the ground side of the device surface of the chip and selectively electrically connected to each source of each transistor device and provides a logical input to a selected transistor device. A plurality of address lines are partially defined by the single layer of conductive material during the chip manufacturing process and are located proximate the ground side the chip, each address line selectively connects a gate of a transistor device and provides a logical input to a selected transistor device. At least one power input is defined by the single layer of conductive material during the chip manufacturing process and is located proximate the power side of the chip, wherein the power input is selectively electrically connected to each drain of each transistor device for providing a logical input to a selected transistor device. The chip has an electrical trace configuration defined by the single layer of conductive material during the chip manufacturing process, electrically connecting the resistive heating elements to the power and ground inputs.
In another embodiment of the invention, a printhead for use in an inkjet printer has a printer controller for controlling the operation of the printer according to printing logic. The printhead includes a heater chip formed from a silicon substrate including a device surface and a substrate surface opposite the device surface which includes a power side and a ground side, wherein the power side and the ground side are in opposing relation on the device surface of the chip. The heater chip includes a plurality of transistor devices located on the device surface of the chip between the power side and the ground side, having connecting regions thereon, wherein each transistor device is selectively enabled according to a logical input from the printer controller. A plurality of resistive heating devices are located on the device surface of the chip, each resistive heating device having a first end and a second end and each resistive heating device is electrically connected to a corresponding transistor device. Each heating device is selectively activated according to the enabling of a respective transistor device based on a logical input from the printer controller. The chip includes a plurality of ink vias etched through the chip from the device surface to the substrate surface which provide ink from an ink reservoir adjacent the substrate surface to one or more of the resistive heating elements, wherein the ink vias are located between the transistor devices and the power side of the heater chip. At least one ground input is defined by a single layer of conductive material during a chip manufacturing process, wherein the ground input is located proximate the ground side of the chip and is electrically connected to each transistor device. The ground input provides a logical input to a selected transistor device. A plurality of address lines partially defined by the single layer of conductive material during the chip manufacturing process are located proximate the ground side of the chip, each address line is selectively connected to a transistor device for providing a logical input to a selected transistor device. The chip also includes at least one power input defined by the single layer of conductive material, located proximate the power side of the chip, wherein the power input is selectively elect

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