Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2011-01-04
2011-01-04
Clark, S. V (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S666000
Reexamination Certificate
active
07863725
ABSTRACT:
Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.
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patent: 7291869 (2007-11-01), Otremba
patent: 2005/0224945 (2005-10-01), Saito et al.
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patent: 2009/0218669 (2009-09-01), Wang
patent: 2010/0019391 (2010-01-01), Strzalkowski
patent: 2010/0038768 (2010-02-01), Kim et al.
Jeon O-soeb
Jong Man-kyo
Lim Seung-won
Son Joon-seo
Clark S. V
Fairchild Korea Semiconductor Ltd.
Townsend and Townsend / and Crew LLP
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