Power device package and method of fabricating the same

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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Details

C257S676000, C257S706000, C257S723000, C257SE23031, C257SE23141, C438S121000, C438S122000

Reexamination Certificate

active

07846779

ABSTRACT:
Provided are a power device package, which can be made compact by mounting semiconductor chips in recesses formed in a substrate and improve operational reliability by rapidly dissipating heat generated during operation to the outside, and a method of fabricating the power device package. The power device package includes: a substrate having a first surface and a second surface opposite to each other, and one or more recesses formed in the first surface; a wiring pattern formed on the first surface of the substrate; one or more power semiconductor chips placed in the recesses and electrically connected to the wiring pattern; a lead frame electrically connected to the wiring pattern; one or more control semiconductor chips electrically connected to the power semiconductor chips to control the power semiconductor chips; and an optional sealing member sealing the substrate, the wiring pattern, the power semiconductor chips, the control semiconductor chips, and at least a part of the lead frame so as to expose the second surface of the substrate.

REFERENCES:
patent: 6181008 (2001-01-01), Avery et al.
patent: 6313598 (2001-11-01), Tamba et al.
patent: 6703703 (2004-03-01), Grant
patent: 7061080 (2006-06-01), Jeun et al.
patent: 7176579 (2007-02-01), Konishi et al.
patent: 7529093 (2009-05-01), Sakamoto
patent: 2004/0070060 (2004-04-01), Mamitsu et al.
patent: 2005/0167789 (2005-08-01), Zhuang

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