Power device driver circuit

Details Power device driver circuit Power device driver circuit

2001-01-19

2002-03-26

Riley, Shawn (Department: 2838)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S333000

Reexamination Certificate

active

06362679

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to techniques for driving devices in half-bridge configurations. More specifically, the present invention provides techniques and circuitry for driving a high side device in a half-bridge configuration into an inductive load in a manner which reduces the effects of parasitic capacitances.
FIG. 1
is a schematic of a driver circuit
100
for the high side device in a half bridge circuit as described in U.S. Pat. No. 4,994,955 for HALF-BRIDGE DRIVER WHICH IS INSENSITIVE TO COMMON MODE CURRENTS issued on Feb. 19, 1991, the entirety of which is incorporated herein by reference for all purposes. The lower half of the schematic is the transmitter portion
76
of a level shifter which converts pulsatile inputs at V
ON
and V
OFF
into current pulses I
ON
and I
OFF
, respectively. The upper half of the schematic is the receiver portion
78
of a high side driver which generates the gate to source voltage for the high side device (not shown) between lines
38
and
40
. Current pulse I
ON
is transmitted alone to place the high side device in a conductive state, while current pulse I
OFF
is transmitted alone to place the high side device in a non-conductive state.
To provide insensitivity to common mode currents I
C
(due to parasitic capacitances
82
), a double differential amplifier comprising transistors T
1
and T
2
and matched resistors R
5
and R
6
is employed. The double differential amplifier produces substantially identical voltages at V
1
and V
2
in response to the common mode currents which will not turn on transistors T
1
and T
2
. By contrast, the current pulse I
ON
flowing only in line
70
turns on T
1
while the current pulse I
OFF
flowing only in line
72
turns on T
2
. The resulting set and reset voltages (V
s
and V
R
) are input to an RS flip-flop
96
which provides the gate drive to the high side device via buffer
106
.
Unfortunately, the solution provided by the circuit of
FIG. 1
does not address other undesirable effects of parasitic capacitance
82
. For example, if the high side device being driven by the circuit of
FIG. 1
drives an inductive load or filter, the resonant current in the inductor can drive the device output toward its positive rail. This positive going output voltage swing, in turn, causes current to flow in parasitic capacitances
82
(these capacitances being charged via either R
1
, R
2
, T
9
, and T
12
). As this current flows, the V
D
supply rail moves up in voltage. That is, V
D
moves up as the output of the high side device approaches its rail because the high side device output is coupled to the V
D
rail via a “bootstrap” capacitance.
As voltages are developed across R
1
and R
2
due to the parasitic currents, the “on” and “off” signals into the high side driver are simultaneously activated. The magnitude of these currents can be such as to active the clamping mechanism implemented with transistors T
11
and T
12
. During the time when T
11
and T
12
are activated, input pulses are ignored. As a result, legitimate “on” pulses could be ignored because of the parasitic currents. This is clearly an undesirable result.
A potential solution to this problem could be to reduce the values of resistors R
1
and R
2
in an attempt to reduce the likelihood of this clamping effect. However, this would require more current to operate the circuit and does not guarantee that the problem is eliminated for all values of output inductors, output transistors, and control signal pulse widths. It should also be noted that eliminating the pulse generators driving V
ON
and V
OFF
alone does not solve the problem as the “on” signal may still be shorter in duration than the duration of the clamping.
It is therefore desirable to provide techniques by which it can be ensured that an “on” signal for the high side device in a half-bridge configuration is never unintentionally ignored.
SUMMARY OF THE INVENTION
According to the present invention, techniques and circuitry are provided which compensate for the effects of parasitic currents in half-bridge driver circuits such that “on” signals are not unintentionally ignored. In addition, and according to specific embodiments, the techniques of the present invention prevent the occurrence of resonance oscillations in the MUTE mode of audio amplifiers which may result, at least in part, from parasitic capacitances. According to a specific embodiments, these goals are achieved by generating a compensating current which effectively cancels the effects of the parasitic current generated in the parasitic capacitance of the driver circuit's input device. This compensating current is generated using a compensating device configured similarly to the driver circuit's input device. The compensating current is generated in the compensating device's parasitic capacitance due to the same condition which causes the parasitic current in the input device. A current mirror is then used to provide the same magnitude current to the parasitic capacitance of the driver circuit's input device, thereby canceling at least part of the effect of the parasitic current.
Thus, the present invention provides a circuit for compensating for a first parasitic current corresponding to a first parasitic capacitance associated with a first switch. A second switch is configured substantially the same as the first switch, the second switch having a second parasitic capacitance associated therewith. A current mirror coupled to the second switch generates a compensating current in response to a second parasitic current corresponding to the second parasitic capacitance. The compensating current compensates for at least a portion of the first parasitic current.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.


REFERENCES:
patent: 4994955 (1991-02-01), Schoofs et al.
patent: 5552731 (1996-09-01), Diazzi et al.
patent: 5742196 (1998-04-01), Fronen et al.

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