Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-03-25
2003-07-22
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06597215
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to a power detector on an integrated circuit, and more particularly, to a power detector composed of metal-oxide-semiconductor (MOS) transistors and capable of increasing integration of an integrated circuit.
2. Description of the Prior Art
In modern information society, there has been a spread in the use of microprocessor systems such as informative appliances, computers, or exchange boards as powerful tools for processing a huge amount of information. For convenience of module designs, most of the microprocessor systems have a plurality of integrated circuits. By assembling these integrated circuits appropriately, the function of a microprocessor system can be realized.
Please refer to FIG.
1
.
FIG. 1
is a function block diagram of a typical integrated circuit
10
. The integrated circuit
10
comprises a power supply
12
for supplying a DC bias voltage required by the integrated circuit
10
, a core circuit
20
, an interface circuit
30
, and a power detector
40
. The core circuit
20
has a clock generator
22
and a plurality of logic gates
24
for executing a data processing function of the core circuit
20
. The power supply
12
includes a first output end
14
and a second output end
16
. The first output end
14
is electrically connected to the power detector
40
and the core circuit
20
, and the second output end
16
is electrically connected to the interface circuit
30
and the power detector
40
. The power supply
12
acquires power from the exterior of the integrated circuit
10
and then supplies a DC core voltage through the first output end
14
and a DC interface voltage through the second output end
16
so as to satisfy the power requirements of the integrated circuit
10
.
Furthermore, the core circuit
20
is used to execute various functions of the integrated circuit
10
, such as data operations and processes. The interface circuit
30
is responsible for tasks such as exchanges of data between the integrated circuit
10
and other external integrated circuits. That is, the interface circuit
30
receives data from the external integrated circuits and transmits the data to the core circuit
20
for processing. Thereafter, the data that has been processed by the core circuit
20
is transmitted to the external integrated circuits through the interface circuit
30
.
For decreasing power consumption so as to help realize high integration and high-speed operations of the integrated circuit
10
, the DC core voltage utilized by the core circuit
20
is lower. On the other hand, the interface circuit
30
uses a higher DC interface voltage so as to achieve a better driving ability and a better noise margin. That is why the power supply
12
has to have two output ends, i.e., the first output end
14
and the second output end
16
, to supply the DC core voltage with a lower value to the core circuit
20
and the DC interface voltage with a higher value to the interface circuit
30
, respectively. Taking a chip composed of various integrated circuits on a motherboard of a computer such as a random access memory (RAM), a central processing unit (CPU), or a north bridge chip responsible for the communications between the RAM and the CPU as an example, the DC interface voltage used for exchanging data between each of the integrated circuits via buses is 3.3V, and the DC core voltage used for internal operations in each of the integrated circuits is 2.5V.
When a microprocessor system is turned on, the power supply
12
of the integrated circuit
10
acquires power from the exterior of the integrated circuit
10
. The power supply
12
starts to set up the DC core voltage with a lower value and supply the DC core voltage to the core circuit
20
, then the power supply
12
sets up the DC interface voltage with a higher value and supplies the DC interface voltage to the interface circuit
30
. In the period of time that the power supply
20
supplies the DC core voltage but has not yet set up the stable DC interface voltage if the core circuit
20
has received the DC core voltage and starts to work, the core circuit
20
cannot execute tasks normally since the DC interface voltage required by the interface circuit
30
has not been set up.
For ensuring the core circuit
20
and the interface circuit
30
of the integrated circuit
10
can be operated simultaneously, the integrated circuit
10
further comprises a power detector
40
for detecting whether the power supply
12
has set up the stable two DC voltage. Only when the power supply
12
has set up the stable DC interface voltage, the interface circuit
30
can execute tasks appropriately and then the core circuit
20
can thus be activated at this time. That is, if the power supply
12
has not set up the DC interface voltage, the power detector
40
cannot trigger the core circuit
20
to work. Conversely, if the power detector
40
detects that the power supply
12
has set up the stable DC interface voltage, the power detector
40
will input a reset signal to the core circuit
20
to inform the core circuit
20
to be ready for startup so as to cooperate with the interface circuit
30
. After receiving the reset signal from the power detector
40
, the core circuit
20
resets the logic gates
24
in the core circuit
20
for resetting the statuses of each of the logic gates
24
. Meanwhile, the clock generator
22
of the core circuit
20
is activated to generate clocks. Then, the integrated circuit
10
can be operated according to the clocks.
Please refer to FIG.
2
.
FIG. 2
is a function block diagram illustrating the prior art power detector
40
used with the power supply
12
and the core circuit
20
in the integrated circuit
10
. The prior art power detector
40
comprises a comparator
44
and a voltage stabilizer
42
. The comparator
44
has two comparison ends
46
and
48
. The comparison end
46
is electrically connected to the power supply
12
for receiving the DC interface voltage from the second output end
16
of the power supply
12
, and the comparison end
48
is electrically connected to an output end of the voltage stabilizer
42
. Furthermore, an output end of the comparator
44
is electrically connected to the core circuit
20
for outputting the reset signal. The voltage stabilizer
42
in the power detector
40
utilizes the DC core voltage from the first output end
14
of the power supply
12
to generate a reference voltage Vref used for comparison and then outputted to the comparison end
48
of the comparator
44
.
When the power supply
12
starts to set up the DC interface voltage, a voltage of the second output end
16
of the power supply
12
is increased from the magnitude of zero and the comparator
44
compares the voltage of the second output end
16
with the reference voltage Vref. If the voltage of the second output end
16
does not exceed the reference voltage Vref, the comparator
44
outputs a low level signal to the core circuit
20
and does not trigger the core circuit
20
. When the voltage of the second output end
16
is increased to exceed the reference voltage Vref, then the power supply
12
can set up the stable DC interface voltage. Meanwhile, the comparator
44
outputs the high-level reset signal to the core circuit
20
and then the reset signal triggers the core circuit
20
.
Furthermore, the voltage stabilizer
42
of the prior art power detector
40
is at least composed of a band-gap circuit. The band-gap circuit has to drive its internal feedback mechanism via current so as to set up the reference voltage Vref. Thus, the voltage stabilizer
42
, i.e., the band-gap circuit is mainly composed of bipolar junction transistors (BJTs), just like the prior art disclosed in U.S. Pat. No. 5,619,163. Therefore, the voltage stabilizer
42
formed on the integrated circuit
10
occupies a lot of area, leading to the integration of the whole integrated circuit
10
being adversely affected. Moreover, since the band-gap circuit is power consumptive, the powe
Hsu Winston
VIA Technologies Inc.
Zweizig Jeffrey
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