Power cut-off device

Details Power cut-off device Power cut-off device

1997-06-16

2000-05-23

Jackson, Stephen W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

361 93, 361115, H02H 300

Patent

active

060672196

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a power cut-off device.


DISCLOSURE OF THE INVENTION

According to the invention there is provided a power cut-off device for protecting a load, the device including a first switching device comprising a field effect transistor having source, drain and gate terminals, and a second switching device having first and second current terminals and a control terminal, wherein the first switching device is cross-coupled to the second switching device with one of the source and drain of the first switching device and one of the first and second current terminals of the second switching device being connected to a common node such that when one switching device is on the other switching device is off and vice versa, and wherein the load is connectable in series with the first switching device such that substantially the entire voltage of the power supply would be applied across the first switching device if the load were short circuited.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a DC power cut-off device according to a first embodiment of the invention,
FIG. 2 is a circuit diagram of an AC power cut-off device according to a second embodiment of the invention,
FIG. 3 is a circuit diagram of a DC power cut-off device according to a third embodiment of the invention, and
FIG. 4 is a circuit diagram of a DC power cut-off device according to a fourth embodiment of the invention.


DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings.
The device according to FIG. 1 comprises a pair of field effect transistors (FETS) T1 and T2 which are cross-coupled so that the drain of each is connected to the gate of the other. FET T1 and FET T2 should have identical electrical characteristics as far as possible. The FET T1 is connected in series with a resistor R1 between a DC voltage supply 10 and ground, and the FET T2 is connected in series with a resistive load 11 to be protected, also between the DC voltage supply 10 and ground.
A capacitor C1 is connected across the source and drain of the FET T2 (at this the point ignore the capacitors C2 and C3) and a fusible link 12 is connected in series with the load 11. A light emitting diode LED 1 and series-connected resistor R2 are connected in parallel with the resistor R1.
In this embodiment the DC voltage supply 10 is 12 volts and the components have the following values:
R1: 420 ohms
R2: 400 ohms
C1: 100 nanofarads
FETs T1 and T2: Beta=0.42
When power is switched on the FET T2 is turned on by the DC voltage applied to the gate of FET T2 via the resistor R1. A capacitor C4 in series with the gate of FET T2 speeds up the operation of the device and ensures that FET T2 turns on while FET T1 remains off. As a result, a small current flows through the RC network comprising capacitor C1 and resistive load 11 at a rate determined by the resistance of the load 11 and the value of the capacitor C1. This causes the voltage to fall at the point A which holds the point B (the gate of FET T1) low. Thus FET T1 is held off and the point C (the gate of FET T2) is high to hold on FET T2 so that the supply 10 is applied to the load 11. This is the normal operating condition of the device, wherein the point A remains low, and thereby holds off the FET T1, all the while the FET T2 is on.
When a short circuit is applied across the resistive load 11 to simulate a fault condition, the point A rises substantially to the voltage of the DC supply 10 at a rate determined by the charge time of the capacitor C1, so that substantially the entire 10 volt supply is placed across the source and drain of the FET T2. Concurrently the current flowing through the FET T2 will increase. However, the 10 volt supply voltage across FET T2 drives the latter into saturation, so that the current through FET T2 is limited to the constant saturation current. The saturation current depends upon the power rating of the FET T2 (essentially its physical size) a

REFERENCES:
patent: 4394703 (1983-07-01), Butcher
patent: 4638396 (1987-01-01), Mukli et al.
patent: 4721869 (1988-01-01), Okado
International Search Report for International Application No. PCT/IE95/00047; Date of Completion--Dec. 22, 1995; Authorized Officer--R. Salm.

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