Power-current measuring circuit in burn-in tester

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S763010, C438S014000, C438S017000, C438S018000

Reexamination Certificate

active

06259267

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power-current measuring circuit for a burn-in tester, and more particularly to a power-current measuring circuit capable of satisfactorily measuring a power current which flows in each semiconductor integrated circuit formed on a wafer disposed in a burn-in tester which performs a burn-in test of the wafer on which the semiconductor integrated circuits have been formed and a power-current measuring method therefor.
2. Description of the Related Art
A process for manufacturing a semiconductor integrated circuit has been performed to maintain the reliability of products by applying power supply voltage to a plurality of semiconductor integrated circuit chips formed on a wafer disposed in a furnace of a constant temperature bath at a wafer level. Moreover, a test pattern signal corresponding to the type of the semiconductor integrated circuit chip is supplied to verify the operation (pass/fail) in a predetermined temperature environment. A burn-in test is performed as described above. The apparatus having a function of determining the pass/fail at the wafer level is referred to as a wafer-level burn-in tester.
The wafer-level burn-in tester incorporates a constant temperature bath with which temperatures and electric signals can be programmed. A multiplicity of test burn-in board (hereinafter called a “TBIB”) on which the wafers are placed are loaded into the constant temperature bath. The TBIB in the constant temperature bath and an external tester are connected to each other through connectors provided for the constant temperature bath. A variety of test signals are transmitted/received through the connectors so that a burn-in test corresponding to the type of the chips placed on the TBIB is performed.
The burn-in test at the wafer level is performed such that measurement of a power current which flows in each semiconductor integrated circuit formed on the wafer is required to perform measurement of the power current for each chip and collective measurement of all of the chips or a plurality of the chips.
FIG. 2
shows an example of a power-current measuring circuit
100
for a conventional wafer level burn-in test. When the power-current measuring circuit
100
shown in
FIG. 2
measures the power current of each chip on the wafer
20
mounted on the TBIB
19
, the output of the power supply circuit
10
(in the foregoing case, a power supply circuit
10
incorporates only large-current measuring power supply circuit
10
a
having a large capacity with which all chips on the wafer
20
can be operated) is connected to each chip on the wafer
20
through a current-detecting resistor
11
and a wafer-chip selection circuit
15
. A wafer-chip selection circuit
15
is connected to a control unit
22
through a bus (BUS). A chip on the wafer
20
instructed with a wafer-chip selection signal supplied from the control unit
22
is selected by wafer-chip selection switches
15
a
to
15
n
accommodated in the wafer-chip selection circuit
15
. Thus, the power current output from the power supply circuit
10
is supplied to the selected chip.
The output of the power supply circuit
10
is as well as connected to a current measuring circuit
13
to which two ends and an input stage of the current-detecting resistor
11
are connected. The current measuring circuit
13
detects the differential voltage generated at the two ends of the current-detecting resistor
11
in accordance with the power current value communicated from the power supply circuit
10
. The current measuring circuit
13
outputs a measured-current signal corresponding to the differential voltage to an A/D converter
18
through an AMP
17
. The A/D converter
18
converts the measured-current signal input from the current measuring circuit
13
and formed into an analog fashion into a digital fashion and outputs a predetermined digital signal indicating the measured current value to the control unit
22
through the bus. Thus, the power current value can be measured.
The above-mentioned measurement of the power current at the wafer level is required to be capable of performing both of the power-current measuring test of all of the chips on the wafer
20
and the power-current measuring test of only one chip. The capacity of the power current which flows in the one chip on the wafer
20
and that of the power currents which flow in all of the chips are different from each other by several hundred times or greater. Therefore, it is preferable that the capacity of the power current of the power supply circuit
10
can precisely be set to be a wide range.
The conventional power-current measuring circuit
100
shown in
FIG. 2
, however, incorporates only the large-current measuring power supply circuit
10
a
having a large capacity with which all chips on the wafer
20
can be operated to serve as the power supply circuit
10
. Therefore, the power currents which are required of both of the power-current measuring test of all chips on the wafer
20
and the power-current measuring test of only one chip and which are different from each other by several hundred times or greater cannot precisely be set. As a result, there arises a problem in that a required resolution accuracy for measuring the power current cannot be realized.
When the measurement resolution of the power-current measuring circuit
100
is adjusted to be capable of measuring the small power current of one chip on the wafer
20
, an A/D converter having an excessively large number of bits and a current detection resistor corresponding to the large electric power is required. The foregoing specifications cannot be realized from a viewpoint of cost reduction.
Therefore, the structure of the conventional power-current measuring circuit
100
for the wafer-level burn-in tester suffers from a problem in that both of the measurement of the large current on the wafer and measurement of the small current of one chip cannot precisely be performed.
SUMMARY OF THE INVENTION
To solve the problems experienced with the conventional power-current measuring circuit for a burn-in tester, an object of the present invention is to provide a power-current measuring circuit for a burn-in tester incorporating a large-current measuring power supply circuit and a small-current measuring power supply circuit as the power supply circuit and arranged to arbitrarily switch the power supply circuit according to the number of chips, which must be measured, so as to be capable of precisely measuring both of a large current and a small current.
According to a first aspect of the present invention, here is provided a power-current measuring circuit for a burn-in tester for use when a burn-in test is performed such that predetermined power currents are, from outside, applied to a plurality of semiconductor integrated circuits formed on a wafer disposed in a constant temperature bath, the power-current measuring circuit for a burn-in tester comprising:
a large-current measuring power supply circuit for supplying power currents which are fed to all of the semiconductor integrated circuits or a plurality of the semiconductor integrated circuits on the wafer;
a small-current measuring power supply circuit for supplying a power current which is fed to at least one semiconductor integrated circuit on the wafer; and
a power-source-output selection circuit which selectively switches output of the large-current measuring power supply circuit and output of the small-current measuring power supply circuit in accordance with the number of semiconductor integrated circuits which are formed on the wafer and which must be tested to supply power currents to the semiconductor integrated circuits which must be tested.
According to the first aspect of the present invention, the power-current measuring circuit for a burn-in tester for use when a burn-in test is performed such that predetermined power currents are, from outside, applied to a plurality of semiconductor integrated circuits formed on a wafer disposed in the

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