Power control means for eliminating circuit to circuit delay dif

Details Power control means for eliminating circuit to circuit delay dif Power control means for eliminating circuit to circuit delay dif

1980-05-16

1982-08-24

Shoop, William M.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

367296R, G05F 146

Patent

active

043463436

ABSTRACT:
An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.
The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.
For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).

REFERENCES:
patent: Re29619 (1978-04-01), Pastoriza
patent: 3271688 (1966-09-01), Gschwind et al.
patent: 3602799 (1971-08-01), Guillen
patent: 3736477 (1973-05-01), Berger et al.
patent: 3743850 (1973-04-01), Davis
patent: 3743850 (1973-07-01), Davis
patent: 3754181 (1973-08-01), Kreitz
patent: 3758791 (1973-09-01), Taniguchi et al.
patent: 3778646 (1973-12-01), Masaki
patent: 3794861 (1974-02-01), Bernacchi
patent: 3803471 (1974-04-01), Price et al.
patent: 3808468 (1974-04-01), Ludlow
patent: 3849671 (1974-11-01), Molack
patent: 3870900 (1975-03-01), Malaviya
patent: 3931588 (1976-01-01), Gehweiler
patent: 3970919 (1976-07-01), Butcher
patent: 3978473 (1976-08-01), Pastoriza
patent: 4004164 (1977-01-01), Crawford, Jr. et al.
patent: 4017750 (1977-04-01), Voorman
patent: 4029974 (1977-06-01), Brokaw
patent: 4065709 (1977-12-01), Sliwa et al.
patent: 4100431 (1978-07-01), Stipanuk
patent: 4145621 (1979-03-01), Colaco
patent: 4160934 (1979-07-01), Kirsch
patent: 4172992 (1979-10-01), Culmer et al.
patent: 4216544 (1980-08-01), Boleda et al.
patent: 4287437 (1981-09-01), Brosch et al.
IBM Technical Disclosure Bulletin, "Speed Normalization of Logic Circuits", J. A. Parisi & J. A. Petrosky, Vol. 17, No. 10, Mar. 1975, pp. 2913-2914.
IBM Technical Disclosure Bulletin, "Current Source Generator", G. Keller et al., Vol. 12, No. 11, Apr. 1970, p. 2031.
IBM Technical Disclosure Bulletin, "Precision Integrated Current Source," A. Cabiedes et al., Vol. 13, No. 6, Nov. 1970, p. 1699.
IBM Technical Disclosure Bulletin, "Voltage Reference Buffer", J. A. Dorler et al., Vol. 14, No. 7, Dec. 1971, p. 2095.
IBM Technical Disclosure Bulletin, "Adjustable Underfrequency-Overfrequency Limiting Circuit", W. B. Nunnery, Vol. 15, No. 6, Nov. 1972, pp. 1927-1929.
IBM Technical Disclosure Bulletin, "Reference Voltage Generator and Off-Chip Driver for Current Switch Circuits", A. Brunin, Vol. 21, No. 1, Jun. 1978, pp. 219-220.
IBM Technical Disclosure Bulletin, "Gated Current Source", J. W. Spencer, Jr., Vol. 21, No. 7, Dec. 1978, pp. 2719-2720.
Electronic Design 6, "Integrated Injection Logic Shaping Up as Strong Bipolar Challenge to MOS", Mar. 15, 1974, pp. 28 & 30.
Electronics, "I.sup.2 L Puts It All Together for 10-Bit A-D Converter Chip", Paul Brokow, Apr. 13, 1978, pp. 99-105.
"Delay Regulation A Performance Concept", Erich Berndlmaier, Jack Dorler, Joseph Mosley, Stephen Weitzel, Proceedings IEEE International Conference on Circuits and Computers, ICCC80, Vol. 2 of 2, edited by N. B. Guy Rabbat, Oct. 1-3, 1980, Ryetown Hilton Inn, Portchester, N. Y., pp. 701-704.
IBM Technical Disclosure, "Chip Performance Regulator Using On-Chip Voltage Controlled Oscillator", K. R. King, Vol. 23, No. 7A, Dec. 1980, pp. 2631-2632.

Affiliated with

Also associated with

Rating

Power control means for eliminating circuit to circuit delay dif does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power control means for eliminating circuit to circuit delay dif, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power control means for eliminating circuit to circuit delay dif will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1438649