Static information storage and retrieval – Powering – Conservation of power
Patent
1990-08-06
1992-05-12
Popek, Joseph A.
Static information storage and retrieval
Powering
Conservation of power
3652335, 365233, 365203, G11C 700
Patent
active
051133733
ABSTRACT:
A power control circuit which provides a means of limiting the active power required by a CMOS EPROM device. A "zero" power direct current (DC) quiescent mode of operation is achieved which enables the EPROM to remain in an active state with outputs active and inputs ready to accept data without power drain to the power supply or battery. On detection of an address transition or chip enable transition, a "power up" sequence occurs. The sense amplifiers, bias circuits and redundancy circuits are preconditioned to accept data. The sense amplifiers and data lines are equalized (precharged) and the bias circuits are powered up. Next, the sense amplifiers are allowed to accept new data from the EPROM core cell. Finally, the data is latched into an output buffer and all circuits are powered down to the "zero" DC power state. The next transition in address location will cause the process to repeat. The present invention enables an EPROM to remain in the active mode with lower overall power drain on a battery.
REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4701889 (1987-10-01), Ando
patent: 4712194 (1987-12-01), Yamaguchi et al.
patent: 4872143 (1989-10-01), Sumi
Advanced Micro Devices , Inc.
Popek Joseph A.
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