Power consumption reduction circuit for clock network

Details Power consumption reduction circuit for clock network Power consumption reduction circuit for clock network

2005-09-08

2008-12-09

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000

Reexamination Certificate

active

07463076

ABSTRACT:
A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.

REFERENCES:
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5594371 (1997-01-01), Douseki
patent: 5726946 (1998-03-01), Yamagata et al.
patent: 5834974 (1998-11-01), Kim
patent: 6049245 (2000-04-01), Son et al.
patent: 6294404 (2001-09-01), Sato
patent: 6327213 (2001-12-01), Ooishi
patent: 6681332 (2004-01-01), Byrne et al.
patent: 6864720 (2005-03-01), Kanazawa
patent: 2 300 985 (1996-11-01), None
patent: 06-029834 (1994-02-01), None
patent: 08-227580 (1996-09-01), None
patent: 08-228145 (1996-09-01), None
patent: 08-321763 (1996-12-01), None
patent: 09-083335 (1997-03-01), None
patent: 10-303370 (1998-11-01), None
patent: 2000-082286 (2000-03-01), None
patent: 2000-082950 (2000-03-01), None
patent: 2003-330568 (2003-11-01), None

Affiliated with

Also associated with

Rating

Power consumption reduction circuit for clock network does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power consumption reduction circuit for clock network, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power consumption reduction circuit for clock network will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4041589