Power conserving phase-locked loop and method

Details Power conserving phase-locked loop and method Power conserving phase-locked loop and method

2000-01-11

2001-07-24

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C327S148000, C327S158000

Reexamination Certificate

active

06265947

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to phase-locked loops, and more particularly to a power conserving phase-locked loop such as may be used as a frequency synthesizer in wireless communications devices.
Phase-locked loops are used to perform a wide variety of tasks, such as frequency synthesis, AM and FM detection, frequency multiplication, tone decoding, pulse synchronization of signals from noisy sources, and regeneration of clean signals, particularly in wireless communications devices. Because batteries power many wireless communications devices that use a phase-locked loop, such as cellular telephones and the like, and because battery lifetime is a major concern for many consumers, new designs for phase-locked loops that reduce power consumption are obviously desirable.
Typically, phase-locked loops include an oscillator for generating the output signal and suitable comparing/locking circuitry. The comparing/locking circuitry outputs a control signal to the oscillator to control the frequency and phase output of the oscillator, thereby ensuring that the output signal is at the desired frequency and phase. The comparing/locking circuitry typically utilizes a bias current to help generate the control signal. In prior art phase-locked loops, the bias current is generated the entire time the phase-locked loop is in an active state (i.e., turned on) and therefore provides a constant drain on the batteries powering the device. While the bias current may be a small fraction of the final output current, it nevertheless represents a significant part of the total current consumption of the phase-locked loop. As such, a new design of phase-locked loop that helps reduce the power drain of the bias current supply would be desirable, particularly in helping to meet consumer demand for improved wireless communications devices with longer battery life.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a power conserving phase-locked loop that may be used for a variety of applications, for example as a frequency synthesizer in a receiver chain of wireless communications mobile terminals and other battery-powered devices where power consumption is a concern. Power savings are achieved by adding a switch which selectively turns on or enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the “lock” in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. In some embodiments, this switching effectuates approximately a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings.


REFERENCES:
patent: 5315270 (1994-05-01), Leonowich
patent: 5351015 (1994-09-01), Masumoto et al.
patent: 5359297 (1994-10-01), Hodel et al.
patent: 5376974 (1994-12-01), Suzuki et al.
patent: 5394444 (1995-02-01), Silvey et al.
patent: 5699020 (1997-12-01), Jefferson
patent: 5783972 (1998-07-01), Nishikawa
patent: 5831483 (1998-11-01), Fukuda
patent: 6097227 (2000-08-01), Hayashi
patent: 0810736A1 (1997-05-01), None
patent: 1-0322197 (1998-04-01), None

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