Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-07-31
2001-07-31
Fears, Terrell W (Department: 2824)
Static information storage and retrieval
Powering
Conservation of power
C365S233100
Reexamination Certificate
active
06269043
ABSTRACT:
FIELD OF INVENTION
The present invention generally relates to a power conservation, and more specifically to a system for conserving processor power by utilization of a snooze mode.
BACKGROUND OF THE INVENTION
It is well recognized that power consumption is a primary concern in battery-powered electronics applications. For example, power consumption is a major concern with embedded processors that are employed in wireless electronics applications, such as laptop computers and handheld devices. These devices require longevity with conservation of battery life. It is further recognized that higher power consumption also results in the generation of higher heat, which can impair the performance of the electronics. Moreover, higher product costs may result from the need to use special packaging and housings in order to dissipating the heat.
With CMOS Application Specific Integrated Circuit (ASIC) devices, the largest factor of power consumption is “dynamic power.” Dynamic power refers to the power consumed during the clocked operation of the device. In this regard, as flip-flops and CMOS logic change logic states (i.e., ‘0’ to ‘1’ or ‘1’ to ‘0’), the associated transistors will consume power. Therefore, running the clock rate of the digital electronics as slowly as possible will reduce dynamic power consumption, since there will be fewer number of logic transitions per unit of time. However, reducing the clock rate of the digital electronics during periods of active device operation may not be an option in some situations. In this regard, high speed performance may demand high speed clocking in many cases. However, clocking a digital electronics device fast when it is in an “idle” state (i.e., not performing useful work) is wasteful of power, since a slower clock speed is suitable under such conditions.
The prior art discloses numerous power reduction techniques including those which use sleep modes with wait states, clock gating, or a selectable clock divider. An object of these prior art techniques is to reduce the switching clock frequency when the processor is in an idle state. However, these techniques require software to determine when to put the device in a sleep mode. Therefore, a watchdog background process typically runs to monitor processor utilization, and indicates when the processor is in an idle state. Upon detecting an idle state, the software must then enable a sleep mode to run the processor at a slow clock speed. In addition, an interrupt handler must be provided to disable the sleep mode and start the processor running again at full clock speed when the idle state has ended (i.e., when an active state has resumed). Consequently, the enable/disable function of the sleep mode requires significant overhead, and in addition typically requires on the order of hundreds of clock cycles to perform the modal switch associated with a change from idle state to active state. Thus, the “sleep modes” utilized in prior art techniques may be termed “heavyweight,” since the act of enabling and disabling the sleep mode requires enormous overhead, including a significant number of clock cycles to perform the switch out of the sleep mode.
Another disadvantage of the “sleep modes” utilized in the prior art that use gated clocks, is the inherent design complexity. This leads to reduction in the overall top speed of the processor and presents clock skew issues among different clock domains.
The present invention addresses these and other disadvantages of the prior art to provide a dynamic and efficient system for clocking a digital electronics device at a fast clock speed only when the device requires the high speed performance (active state), and to clock the device at a slower clock speed at other times.
SUMMARY OF THE INVENTION
According to the present invention there is provided a power conservation system comprising: (a) clock generation means for generating a first clock signal having a first frequency; (b) wait state generation means for generating a wait state for modifying the first frequency; (c) enabling means for detecting at least one first operating condition of an associated electronic device, and generating an enable signal for enabling the wait state generation means to generate the wait state for modifying the first frequency; and (d) disabling means for detecting at least one second operating condition of the associated electronic device, and generating a disable signal for disabling the wait state generation means.
In accordance with another aspect of the present invention, there is provided a power conservation system comprising: (a) a clock generating circuit for generating a first clock signal having a first frequency; (b) a wait state circuit for generating a wait state for modifying the first frequency; (c) a first condition detecting circuit for detecting at least one first operating condition of an associated electronic device, and generating an enable signal for enabling the wait state generation circuit to generate the wait state for modify the first frequency; and (d) a second condition detecting circuit for detecting at least one second operating condition of the associated electronic device, and generating a disable signal for disabling the wait state generation means.
In accordance with still another aspect of the present invention, there is provided a method for conserving power consumed during clocked operation of an associated electronic device, the method including the steps of: (a) generating a first clock signal operating at a first frequency; (b) modifying the first clock signal to operate at a second frequency, in response to detection of at least one first operating condition of the associated electronic device; and (c) returning the first clock signal to the first frequency, in response to detection of at least one second operating condition of the associated electronic device.
An advantage of the present invention is the provision of a power conservation system for modifying a clock speed, which allows for quick and efficient changes in the operating clock speed between slow speed (snooze mode) and full speed (regular mode), depending upon the operating state of an associated processor.
Another advantage of the present invention is the provision of a power conservation system that does not require the overhead of prior art “sleep mode” systems, thus moving between regular mode to snooze mode quickly and efficiently.
Still another advantage of the present invention is the provision of a power conservation system that can utilize context state information provided by a processor with context switching hardware, in order to modify the processor clock speed accordingly.
Still other advantages of the invention will become apparent to those skilled in the art upon a reading and understanding of the following detailed description, accompanying drawings and appended claims.
REFERENCES:
patent: 6188636 (2001-02-01), Salomon
Arter & Hadden LLP
Cisco Technology Inc.
Fears Terrell W
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