Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Patent
1996-03-11
1999-01-12
Saras, Steven J.
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
345 95, G01G 500
Patent
active
058596321
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to a power circuit, a liquid crystal display device incorporating this power circuit, and electronic equipment incorporating either the power circuit or the liquid crystal display device.
2. Related Art
FIG. 18 is a schematic diagram of electrodes of a liquid crystal panel that is multiplex driven. To simplify the description, this liquid crystal panel includes nine segment electrodes and six common electrodes. Each rectangle in this figure represents an electrode formed in the liquid crystal panel, and these electrodes are divided into segment electrodes (SEG1 to SEG9) and common electrodes (COM1 to COM6), depending on the signals that are applied thereto. The square shaded portion at each intersection of electrodes represents a display dot. To ensure that each display dot operates as a capacitor, a capacitor links the segment electrode and common electrode at a corresponding display dot.
Voltage levels V0 to V5 that are necessary for driving liquid crystal elements by a multiplex-driven method with a high duty ratio (six-level drive method) generally satisfy the relationships V0-V1=V1-V2 =V3-V4=V4-V5 and V0>V1>V2>V3>V4>V5, as shown in FIG. 19. In this case, it is assumed that V0 to V2 are a first group of drive voltages and V3 to V5 are a second group of drive voltages. The voltage range of the first group of drive voltages V0 to V2 does not overlap the voltage range of the second group of drive voltages V3 to V5, and is separate therefrom.
FIG. 19 shows examples of signal waveforms applied to the segment and common electrodes. The signal applied to a segment electrode generally switches between voltage levels V3 and V5 during the period of a frame 0 (hereinafter called FR0). Similarly, the signal switches between voltage levels V0 and V2 during the period of a frame 1 (hereinafter called FR1). This switching of the voltage level at the segment electrode depends on the pattern to be displayed.
At the same time, the signal applied to a common electrode is at voltage level V4 during a non-selected state in the FR0 period, or at voltage level V0 during a selected state. Similarly, the signal is at voltage level V1 during the non-selected state in the FR1 period, or at voltage level V5 during the selected state. The period during which a common electrode is in the selected state differs for all of the common electrodes, and it is not possible for a plurality of common electrodes to be simultaneously selected. Voltage levels are inverted between the FR0 and the FR1 periods, to drive the liquid crystal in an alternating fashion.
The switching of the voltage levels at the segment and common electrodes is in accordance with the charging and discharging of capacitances existing within the liquid crystal panel. This means that currents flow through the liquid crystal panel between each of the voltage levels V0 to V5. These currents are hereinafter called panel currents.
The voltage level of each segment electrode switches between V0 and V2 (in the FR1 period) or V3 and V5 (in the FR0 period). For a large proportion of the time, each common electrode is in a non-selected state, so the voltage level thereof is mostly at V1 (in the FR1 period) and at V4 (in the FR0 period). This means that a panel current caused by a switch in voltage level at a segment electrode (hereinafter called a segment panel current) flows mainly between the first group of drive voltages V0, V1, and V2 or the second group of drive voltages V3, V4 and V5. Similarly, a panel current caused by a switch in voltage level at a common electrode (hereinafter called a common panel current) flows mainly between V5 and a voltage within the first group of drive voltages V0, V1, and V2, or between V0 and a voltage within the second group of drive voltages V3, V4, and V5.
A power circuit that supplies the above panel currents is disclosed as a prior-art method in Japanese Patent Application Laid-Open No. 2-150819. The configuration thereof is shown in FIG. 20. In this figu
REFERENCES:
patent: 5198767 (1993-03-01), Haight
patent: 5343217 (1994-08-01), Kim
patent: 5402142 (1995-03-01), Okada et al.
patent: 5404150 (1995-04-01), Murata
patent: 5510814 (1996-04-01), Ise
Saras Steven J.
Seiko Epson Corporation
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