Power circuit and clock signal detection circuit

Details Power circuit and clock signal detection circuit Power circuit and clock signal detection circuit

1998-10-07

2001-04-17

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S544000

Reexamination Certificate

active

06218893

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power circuit and a clock signal detection circuit, and especially relates to those which are applicable to a semiconductor memory device.
2. Description of the Related Art
With the recent remarkable advancement in the micro-miniaturization technique of the semiconductor memory device provided with an extremely large memory capacity, a new problem has come out that the dielectric strength or the withstand voltage of the memory device is more weakened or lowered. In order to manage this problem, the semiconductor memory device such as a synchronous DRAM it (SDRAM) which synchronously operates with the clock signal, is provided with a power circuit which serves to reduce an externally supplied voltage such as 3.3 V to a voltage 2.7 V for use in the memory device.
In the operation of the memory device, as is known, there is a situation in which after receiving the input of an active command, SDRAM is kept in a waiting position i.e. in an active standby mode, for a certain period of time until the next command such as data read or write command is inputted thereto. In order to save the power consumption in such a situation, some measures have been taken so far, for instance interrupting the supply of the clock signal to SDRAM, or invalidating the clock signal by the clock enable signal to stop all the circuits operable with the clock signal.
The power consumption by SDRAM is also increased while SDRAM is in operation for reading/writing data, and this causes the internal voltage to be varied. In order to manage this internal voltage variance, the prior art power circuit which is built in SDRAM is constituted to monitor the internal voltage variance and to immediately compensate it, if any, so as to maintain the constant and stable power supply to the circuit connected with SDRAM.
However, in order that the built-in power circuit may quickly respond to the internal voltage variance, it is needed that the built-in power circuit is additionally provided with another circuit such as an amplifier circuit for amplifying the output power thereof, thereby increasing the internal current in the circuits constituting the power circuit. Consequently, this results in increase in the internal current totally spent by the whole built-in power circuit including the added amplifier circuit. Thus, this raises the power consumption by the entire SDRAM, which is against the purpose of saving the power after all.
Furthermore, while SDRAM stays in the active standby mode, it does not carry out any operation for reading/writing data. In spite of this, the prior art built-in power circuit has to keep the internal current at an increased level, because the built-in power circuit has to quickly respond at any time to the possible internal voltage variance which might be caused by the coming operation of reading/writing data. Consequently, SDRAM has to unnecessarily waste the power whenever it is in the active standby mode.
SUMMARY OF THE INVENTION
Accordingly, the invention has been made in view of the problems experienced in the prior art built-in power circuit as described in the above, and a object of the invention is to provide an power circuit which makes it possible to output the constant and stable power, and at the same time to achieve the effective power saving.
Furthermore, the second object of the invention is to provide a clock signal detection circuit which detects the clock signal and supplies the detected signal to the power circuit which is built in the semiconductor memory such as SDRAM, thereby judging if SDRAM is in the active standby mode or not.
In order to solve the problems as mentioned above, according to the first aspect of the invention, there is provided a power circuit which is provided in the semiconductor memory and transforms the external voltage applied to the semiconductor memory into a predetermined internal voltage. This power circuit includes a voltage transformation portion for transforming the external voltage into the internal voltage; an internal voltage regulation portion which monitors the value of the internal voltage and outputs a control signal, which controls the voltage transformation in response to the variance of the internal voltage, to the voltage transformation portion; and a response time regulation portion which regulates the output response time of the above voltage transformation control signal based on the mode signal corresponding to a plurality of operational modes of the semiconductor memory. According to the constitution of the power circuit as mentioned above, the response speed of the internal voltage regulation portion can be set in response to the variance of the internal voltage, based on the operational mode of the semiconductor memory. More specifically, if the semiconductor memory operates in the data write/read mode which tends to increase the variance of the internal voltage, the varied internal voltage can be instantaneously returned to its predetermined value by increasing the response speed of the internal voltage regulation portion. Contrary to this, if the semiconductor memory operates in the mode which hardly causes the variance of the internal voltage, it is possible to decrease the response speed of the internal voltage regulation portion.
Since the output response time of the response time regulation portion can be regulated by means of controlling the value of the internal current in the internal voltage regulation portion, the internal current of the power circuit is optimized in correspondence with the operational mode of the semiconductor memory. Consequently, there is achieved the reduction of the power consumption by the semiconductor memory.
Since the internal voltage regulation portion monitors the value of the internal voltage referring to the value of a reference voltage, the value of the internal voltage can be altered with ease by regulating the reference voltage.
If a plurality of operational modes of the semiconductor memory includes at least an active standby mode, the power consumption of the power circuit can be reduced by lowering the response speed of the internal voltage regulation portion during the active standby mode.
The above-mentioned power circuit may be provided with a clock signal detection circuit which detects a clock signal in the semiconductor memory and is able to output the detection result thereof as the active standby mode signal. With this, the operational mode, especially the standby mode of the semiconductor memory can be discriminated with ease by detecting the clock signal.
The clock signal detection circuit may include a charge/discharge circuit which charges the output node thereof, synchronized with the rising edge and the falling edge of the clock signal, and if the discharge time of the output node of the charge/discharge circuit is set longer compared with the period of said clock signal, the clock signal detection circuit ensures the clock signal detection with the simple circuit structure.
The clock signal detection circuit may be provided with a first one-shot pulse generating circuit which generates a one-shot pulse, synchronized with the rising edge of the clock signal, and a second one-shot pulse generating circuit which generates a one-shot pulse, synchronized with the falling edge of the clock signal. The operation of the charge/discharge circuit can be stabilized with provision of these one-shot pulse generating circuits.
The clock signal detection circuit may be constructed to include a first charge/discharge circuit which charges the output node thereof, synchronized with the falling edge of the clock signal, and starts discharging the same, synchronized with the rising edge of the clock signal; a second charge/discharge circuit which charges the output node thereof, synchronized with the rising edge of said clock signal, and starts discharging the same, synchronized with the falling edge of said clock signal; and an exclusive NOR gate, of which the first input terminal is connected with

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