Power buss inhibit through data input/output lines

Details Power buss inhibit through data input/output lines Power buss inhibit through data input/output lines

2000-05-31

2002-09-17

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C327S525000, C327S565000

Reexamination Certificate

active

06452770

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to high speed digital data processing arrangements and, more particularly, to CMOS integrated circuit card configurations operating upon a received data input stream.
2. Description of the Related Art
High speed, digital data processing arrangements employing CMOS devices typically operate with supply voltages of 5 volts. When used in system configurations, input/output data busses conventionally run between individual integrated circuit cards. When a system fails, investigation is needed to locate the defective integrated circuit card, and to replace it. Where, instead, the integrated circuit card continues to operate—albeit outside the range for which it was designed—, other circuit cards frequently become loaded, and the circuits become unable to communicate intelligently with one another. System operation can then be down for hours, or even days, until the problem is cleared.
Analysis has shown that haphazard operation can occur when the power buss fuse blows on an individual integrated circuit card while the card continues to receive incoming data. Such analysis revealed that this was due to the intrinsic substrate diode incorporated in the CMOS manufacture as a safety precaution. There, with the intrinsic diode at each integrated circuit input, when the power buss was open, the decoupling capacitors charged through the data lines, and to a voltage which depended upon the number of integrated circuits connected to the power buss and upon the frequency of the data pulse transmissions. Thus, even where no supply voltage was being provided (as the fuse was open-circuited), the decoupling capacitors charged to some intermediate voltage, but less than the 5 volts or so specified by the integrated circuit manufacturer for guaranteed circuit operation to follow. A degree of integrated circuit operation resulted, but one which was indeterminate, indefinite and non-predictable.
SUMMARY OF THE INVENTION
As will become clear from the following description, correct charging of the decoupling capacitor essentially is attained by with the invention disconnecting from the power buss that power pin of the integrated circuit to which the data input stream is applied, while continuing to directly connect the power buss to the power pin of the remaining individual integrated circuits on the CMOS card. In accordance with the invention, and as will be seen, at that input stage, a diode is connected instead, with its anode connected to the power buss and with its cathode connected to the power pin. In a preferred embodiment of the invention, the diode is in the form of a Schottky diode with its anode at the power buss and its cathode at the power pin, selected to exhibit a forward voltage drop of the order of 0.3 volts for a 5 volt or so power buss voltage. Depending upon the supply voltage to which the CMOS integrated circuits are designed, the forward voltage drop of the diode selected may be greater or less, chosen to couple that voltage from the power buss sufficient to operate the integrated circuit transistors at their manufacturer recommended ranges of performance.
As will be seen, a pair of arrangements for the Schottky diode inclusion are described—one, operable with a CMOS integrated circuit card of the type typically manufactured, with the power pins of the individual integrated circuits all directly connected to the common power buss. Utilizing the teachings of the invention in this arrangement, a circuit designer simply removes the trace connection on the circuit card for that stage (or stages) receiving the input data, and externally connecting instead the Schottky diode from the decoupling capacitor to the power pin of the stage (or stages).
In the second arrangement, on the other hand, the typical CMOS integrated circuit manufacture is modified to include the Schottky diode directly on the monolithic device, included between the common power buss and the power pin for each individual integrated circuit, and paralleling the diode with a switch, to be either short circuited where the individual stage is not receiving the data input stream, or to be open circuited (and, therefore, inserting the Schottky diode) where the stage is to be so used. In this arrangement, as described below, the switch is in the form of a fuseable link, to be burned open by the circuit designer at those locations where the input data stream is not being operated upon.
Thus, in these manners, the teachings of the invention can be incorporated by the integrated circuit manufacturer in redesigning the integrated circuit device; or by the circuit designer in removing the trace between the power pin and power buss on the card, and adding instead, the Schottky diode or other reverse-bias diode of the invention to prevent the data pulses from charging the decoupling capacitor(s).


REFERENCES:
patent: 4871927 (1989-10-01), Dallavalle
patent: 5568060 (1996-10-01), Bartholomay et al.
patent: 5585792 (1996-12-01), Liu et al.
patent: 5708771 (1998-01-01), Brant et al.
patent: 6266290 (2001-07-01), Sredanovic et al.

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