Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Regenerating or restoring rectangular or pulse waveform
Reexamination Certificate
2000-06-07
2001-07-24
Mai, Son (Department: 2818)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Regenerating or restoring rectangular or pulse waveform
C327S165000, C327S291000, C327S551000
Reexamination Certificate
active
06265920
ABSTRACT:
BACKGROUND
In many digital systems, the interconnection bandwidth between chips is a critical limitation on performance. Historically, inter-chip signaling has performed much more slowly than on-chip processing. As a result, much effort has been focused on increasing bandwidth of signaling between chips since it represents a significant bottleneck for system performance. However, the same problems may develop for signals internal to the chip. As technology continues to scale smaller, the problems with intra-chip signaling will become more pronounced. Without improvements to high speed digital signaling techniques, intra-chip signaling will prove to be a limit to overall system performance.
An example of an ideal digital signal
10
is shown in
FIG. 1
a
. A midpoint
12
is shown that serves to define the change in the value of the data bit. In the lower region
10
, the data bit has a value of “0”. While in the upper region
14
, the data bit has a value of “1”. This type of digital scheme with a mid-point
12
is referred to as a single-end signal design.
FIG. 1
b
shows a more realistic view of the waveform of the same digital signal
18
. The midpoint
12
as well as the upper
14
and lower
16
regions are the same. However, the signals are subjected to some suppression of the signal's peak value called attenuation. The attenuation is particularly pronounced in the case of a single “1” in a field of “0”s. In some instances, the attenuated signal barely reaches the midpoint
12
, which results in a very low probability of detection. The attenuation is primarily caused by skin-effect resistance and dielectric absorption by the transmission line. However, the skin-effect resistance is usually the dominant factor. In any case, the magnitude of the attenuation will increase with the frequency.
With a typical broadband signal, the superposition of an unattenuated low frequency signal component with attenuated high frequency signal components causes intersymbol interference that reduces the maximum frequency at which the system can operate. During this intersymbol interference, or hysteresis, the signal “remembers” its previous state. The problem is not so much the magnitude of the attenuation as it is the interference caused by the frequency dependent nature of the attenuation. The interference comes from noise sources such as receiver offset, receiver sensitivity, crosstalk, reflections of previous data bits, and coupled supply noise.
The effects of such interference are shown in
FIGS. 2
a
and
2
b
. Both of these figures show a differential digital signal design. The differential signal differs from the single end signal in that it provides complementary high and low signals instead of a single signal.
FIG. 2
a
shows an attenuated differential signal
20
. The high signal component
22
and the low signal component
24
intersect to form an eye
26
. The amplitude of the eye
28
is obviously dependent on the amount of attenuation of each signal. Only a few decibels (dB) of frequency dependent attenuation can be tolerated by such a signaling system before intersymbol interference overwhelms the signal.
FIG. 2
b
shows a differential signal with deterministic jitter
30
. The amount of offset
32
of jitter affects the width of the eye and may possibly eliminate the eye entirely as shown in
FIG. 2
b
. Jitter is caused by fluctuations in the sampling clock, fluctuations in the receiving clock, and delay variations in the signal path. Each of these sources of jitter are primarily the result of power supply modulation and crosstalk induced delay variation.
One solution to the problem of intersymbol interference is equalization of the signal by pre-emphasizing the high-frequency components of the signal before transmission. This will significantly eliminate the interference. The effects of equalization are shown in
FIGS. 3
a
and
3
b
.
FIG. 3
a
shows an unequalized signal that is similar to that shown in
FIG. 2
a
. As shown previously, the amplitude
28
of the eye
26
of the signal is reduced due to the frequency dependent attenuation.
FIG. 3
b
shows a signal
36
where both the high signal component
22
and the low signal component
24
have been equalized. As can be clearly seen, the amplitude
40
of the eye
38
is increased while the full width of the eye
38
is maintained.
BRIEF SUMMARY OF INVENTION
In one embodiment, the invention is a method for pre-emphasizing an intra-chip digital signal comprising: inputting a data bit from an on-chip source, a complement of the data bit, a previous data bit from an on-chip source, and a complement of the previous data bit to a predriver; pre-emphasizing a transition in value between the data bit and the previous data bit with the predriver; and outputting an equalized digital signal from the predriver to an on-chip destination.
In another embodiment, the invention is a circuit for pre-emphasizing an intra-chip digital signal comprising: a predriver which receives a data bit from an on-chip source, a complement of the data bit, a previous data bit from an on-chip source, and a complement of the previous data bit, wherein the predriver pre-emphasizes a transition in value between the data bit and the previous data bit; and an output stage which outputs an equalized digital signal to an on-chip destination.
In another embodiment, the invention is a circuit for pre-emphasizing an intra-chip digital signal comprising: means for receiving a data bit from an on-chip source, a complement of the data bit, a previous data bit from an on-chip source, and a complement of the previous data bit; and means for pre-emphasizing a transition in value between the data bit and the previous data bit, and outputting an equalized digital signal to an on-chip destination.
In another embodiment, the invention is a single sheet of silicon comprising: a predriver which receives a data bit from an on-chip source, and a previous data bit from an on-chip source, wherein the predriver pre-emphasizes a transition in value between the data bit and the previous data bit; and an output stage which outputs an equalized digital signal to an on-chip destination.
The advantages of the disclosed invention may include the use of a circuit for pre-emphasizing a high frequency intra-chip signal. The circuit may include a single or dual predriver stage. A single predriver stage allows for a reduction of power dissipation, a reduction in required area on the chip, and an increase in the bandwidth.
REFERENCES:
patent: 4637036 (1987-01-01), Kobari
patent: 4791590 (1988-12-01), Ku et al.
patent: 5300820 (1994-04-01), Sayama et al.
patent: 5396109 (1995-03-01), Oshiba
patent: 5578943 (1996-11-01), Sasaki
patent: 5578944 (1996-11-01), Sasaki
patent: 5787261 (1998-07-01), Osaka et al.
patent: 5923201 (1999-07-01), Suzuki
W. Dally and J. Poulton, “Transmitter Equalization for 4Gb/s Signalling”, undated, 10 pages.
J. Poulton, W. Dally and S. Tell, “A Tracking Clock Recovery Receiver for 4Gb/s Signaling”, undated, 13 pages.
W. Dally, J. Poulton and S. Tell, slides from presentation: “Multi-gigabit signaling with CMOS”, May 12, 1997, 26 pages.
Mai Son
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
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