Power and ground buss layout for reduced substrate size

Details Power and ground buss layout for reduced substrate size Power and ground buss layout for reduced substrate size

2007-03-27

2007-03-27

Stephens, Juanita D. (Department: 2853)

Incremental printing of symbolic information

Ink jet

Ejector mechanism

C347S058000

Reexamination Certificate

active

10956939

ABSTRACT:
A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.

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