Power amplifier with an idle current trimmed and a method of tri

Amplifiers – With semiconductor amplifying device – Including field effect transistor

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Details

330296, H03F 316, H03F 304

Patent

active

059865032

ABSTRACT:
A power amplifier including an FET and a gate bias circuit having a variable resistor (VR) and a method of trimming the VR in the power amplifier are disclosed. The VR is trimmed to make the bias voltage to a pinch-off voltage of the FET. A first current in the pinch-off voltage condition from a bias supply voltage is measured. The VR is adjusted with a second current from the bias supply voltage measured. A difference between the first and second drain current values is calculated and a resistance of the VR is determined to make the difference within a reference. A second VR may be connected to the VR in parallel to make trimming the bias voltage easier or more accurately. The second VR may comprise a printed circuit pattern which shows 0.OMEGA. for the pinch-off condition and the printed circuit pattern also provides the infinite resistance when it is cut to adjust the VR. Another power amplifier including a memory and a D/A converter for generating the gate bias voltage is also disclosed. The memory stores data making the FET in the pinch-off condition to measure the first current, a set of data varying the second current to adjust the VR and can store the data making the difference within the predetermined value. In the case of multi-stage, trimming is performed from one of stages of which reference is smallest.

REFERENCES:
patent: 5060294 (1991-10-01), Schwent et al.
patent: 5250912 (1993-10-01), Fujita
patent: 5675290 (1997-10-01), Tsukahara et al.
patent: 5745857 (1998-04-01), Maeng et al.

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