Power amplifier having low gate oxide stress

Details Power amplifier having low gate oxide stress Power amplifier having low gate oxide stress

2005-05-03

2005-05-03

Nguyen, Khanh V. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including protection means

C330S311000

Reexamination Certificate

active

06888410

ABSTRACT:
A power amplifier includes an input transistor, an input bias circuit, an output transistor, and a power down circuit. The input transistor includes a gate, a drain, and a source, wherein the source of the input transistor is coupled to a supply voltage return and the gate of the input transistor is operably coupled to receive an outbound radio frequency (RF) signal. The input bias circuit is operably coupled to provide an enabling bias voltage to the gate of the input transistor during transmit mode and to provide a disabling bias voltage to the gate of the input transistor during power down mode. The output transistor includes a gate, a drain, and a source, wherein the drain of the output transistor is coupled to provide an output of the power amplifier and the source of the output transistor is coupled to the drain of the input transistor. The power down circuit is operably coupled to provide an output enabling bias voltage to the gate of the output transistor during the transmit mode and to provide an output disabling bias voltage to the gate of the output transistor during the power down mode, wherein the output disabling bias voltage is of a value to distribute gate oxide stress between the input transistor and the output transistor.

REFERENCES:
patent: 6392490 (2002-05-01), Gramegna et al.
patent: 6542036 (2003-04-01), Kusachi
patent: 20040102173 (2004-05-01), Darabi

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