Power amplifier arrangement and method for data signal interface

Amplifiers – With semiconductor amplifying device – Including particular power supply circuitry

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341144, H03F 304, H03M 166

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active

058983422

ABSTRACT:
An arrangement and method using power more efficiently for signal amplification. The approach is particularly advantageous in application environments where digital information is converted to the analog domain and carried at a variety of different magnitudes. One embodiment involves a signal processing and amplifying arrangement including a digital-to-analog converter, an amplifier and a control signal selection circuit. The digital-to-analog converter receives a digital signal and outputs, in response to the digital signal, an analog signal. The amplifier amplifies the analog signal using power received from a high-level supply and a low-level supply, at least one of which has a variable setting in response to a control signal. The amplifier is configured and arranged to amplify the analog signal. The control signal selection circuit is responsive to the digital signal, and is used for selecting the control signal to cause the supplies to the amplifier to track the expected magnitude of the analog signal.

REFERENCES:
patent: 4688001 (1987-08-01), Dijkmans et al.
patent: 4721919 (1988-01-01), LaRosa et al.
patent: 5585795 (1996-12-01), Yuasa et al.
Sampei et al., "Highest Efficiency and Super Quality Audio Amplifier Using MOS Power FETs in Class G Operation", IEEE Transactions on Consumer Electronics, CE(24)3, pp. 300-307 (1978).
Raab et al., "Average Efficiency of Class-G Power Amplifiers", IEEE Transactions on Consumer Electronics, CE32(2), pp. 145-150 (1986).

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